Design Methodologies for Heterogeneous 3-D Integrated Systems

UoM administered thesis: Phd

  • Authors:
  • Ioannis Papistas

Abstract

Design techniques for heterogeneous three-dimensional (3-D) integrated circuits are developed in this thesis. Heterogeneous 3-D integration is a platform for multifunctional, high performance, and low power electronics. For the advancement of heterogeneous 3-D ICs, contactless solutions are investigated to implement inter-tier communication between tiers manufactured with disparate processes and heterogeneous technologies. Two challenges for the development of contactless inter-tier communication are addressed, the design of energy efficient, heterogeneous inductive link transceivers and the impact of crosstalk noise due to the on-chip spiral inductors. Inter-tier communication between circuits fabricated with disparate technologies requires transceivers capable of operating at dissimilar voltages. A low power transceiver design methodology is proposed exploiting the difference in the core voltage between disparate manufacturing processes in a 3-D system in package. A transceiver is designed to provide inter-tier communication between a sensing layer, designed in a commercial 0.35 µm process and a processing layer, designed in an advanced 65 nm process. A significant gain in the power consumed by the transceiver is shown compared to equivalent state-of-the-art prototypes, profiting by the tradeoff between the core voltage and sensing ability of the transceiver circuit in each process. Due to their wireless nature, however the use of inductive links introduces crosstalk noise due to the coupling between the on-chip inductor and on-chip interconnects in the vicinity of the inductor. The noise caused by the inductor on the power distribution network of an integrated system is explored, analysed, and modelled through electromagnetic simulations. The spatial distribution of the noise is described for several power distribution topologies to determine the preferred placement solution for the power and ground network in the vicinity of the inductor, considering the impact on other sources of noise, such as the resistive drop. Depending upon the power distribution network topology, the induced noise can be reduced up to 70% when the additional noise caused by the inductive link is considered by the routing algorithm. Additionally, a methodology utilising an analytic model is proposed for the evaluation of the crosstalk noise without resorting to electromagnetic simulations. A closed-form magnetostatic model is developed to assess the mutual inductance between the on-chip inductor and the power distribution network. Utilising the mutual inductance model, the crosstalk noise is evaluated with SPICE simulations. A signifcant benefit in speedup is achieved, up to four orders of magnitude for determining the mutual inductance and up to 4.7× for the assessment of the crosstalk noise. The accuracy of the model is within 10% of the electromagnetic simulation.

Details

Original languageEnglish
Awarding Institution
Supervisors/Advisors
Award date1 Aug 2018