Design and Analysis of High Performance DC-DC Converters with SiC Technology

UoM administered thesis: Phd

  • Authors:
  • Md Rishad Ahmed

Abstract

Circuit level analytical models are developed for rapid and accurate evaluation of hard-switching, soft-switching, and dv/dt-induced false turn events of Silicon Carbide (SiC) MOSFETs using only datasheet parameters. The models include the high-frequency parasitic components in the circuit and incorporate the nonlinearities in the junction capacitances of the devices by fitting their nonlinear capacitance curves to a simple equation. The analytical models were solved numerically using MATLAB and the results showed a very good match with the experiments and LTspice simulations. The proposed models were more accurate than LTspice models in predicting the switching losses and required one third of the computation time. The analytical models are evaluated at 25 °C and 125 °C and their experimental validation is described. The model is extended to include the reverse recovery effect of a SiC MOSFET body diode to investigate the dynamic performance of the body diode in hard-switching operation. The dv/dt-induced false turn-on conditions of the SiC MOSFET are predicted analytically and validated experimentally. It was observed that consideration of nonlinearities in the junction capacitances ensures accurate prediction of false turn on. The soft-switching waveforms were also compared with the hard-switching ones both analytically and experimentally to illustrate the advantages of soft-switching in practical converter applications. It was found that soft-switching can significantly reduce the switching losses and could enable higher operating switching frequency for SiC MOSFETs. Two soft-switching DC-DC boost topologies are investigated to extend the switching frequencies of 1200 V, 100 A SiC MOSFET modules beyond the state-of-the-art, 75 kHz. Auxiliary circuits are introduced to the switching legs of the dual-interleaved boost converter to ensure snubber assisted zero voltage zero current (SAZZ) switching of all the semiconductor devices. In the conventional SAZZ topology each auxiliary circuit contains a snubber capacitor, a SiC MOSFET, a SiC Schottky diode and an auxiliary inductance. The auxiliary inductance is replaced by a pulse transformer and a Schottky diode in the modified SAZZ topology. In both topologies, the snubber capacitors and output capacitances of the main devices are discharged prior to turn on by resonating with the auxiliary inductance, eliminating turn on losses. Furthermore, the turn off losses are significantly reduced since the energy stored in the device output capacitance at turn off is recovered at turn on. The design equations are derived and the timing requirements for the soft-switching operation are established for both topologies. A SiC prototype of the conventional SAZZ topology operated at 12.6 kW, 112 kHz, 170-400 V, reducing the switching losses by 57% compared with hard-switching. However, the soft-switching range of the converter was limited to duty ratios above 50%. The modified SAZZ topology overcomes the limitation by replacing the auxiliary inductor with a pulse transformer with 1 : 2 turns ratio and ensures soft-switching for all duty ratios. The SiC prototype using the modified SAZZ topology operated at 20 kW, 112 kHz, 320-600 V, reducing the switching losses by 75% compared with the hard-switching operation.

Details

Original languageEnglish
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Award date1 Aug 2018