Prof Piotr Dudek

Professor of Circuits and Systems

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Publications

  1. Published

    Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters

    Mroszczyk, P. & Dudek, P., 2013, 11th IEEE International New Circuits and Systems Conference, NEWCAS 2013. 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  2. Published

    The accuracy and scalability of continuous-time Bayesian inference in analogue CMOS circuits

    Mroszczyk, P. & Dudek, P., 2014, IEEE International Symposium on Circuits and Systems, ISCAS 2014. p. 1576-1579

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  3. Published

    Gradient-descent-based learning in memristive crossbar arrays

    Nair, M. V. & Dudek, P., Jul 2015, International Joint Conference on Neural Networks, IJCNN 2015 . IEEE, 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  4. Published

    Practical Gradient-Descent for Memristive Crossbars

    Nair, M. V. & Dudek, P., Nov 2015, International Conference on Memristive Systems, MEMRISYS 2015. IEEE

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  5. Published

    A field programmable array core for image processing

    Walsh, D. & Dudek, P., Feb 2012, Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA'12. Association for Computing Machinery, p. 266-266

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  6. Published

    A compact FPGA implementation of a bit-serial SIMD cellular processor array

    Walsh, D. & Dudek, P., 2012, International Workshop on Cellular Nanoscale Networks and their Applications|Int. Workshop Cell. Nanoscale Netw. Appl..

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  7. Published

    An event-driven massively parallel fine-grained processor array

    Walsh, D. & Dudek, P., Jun 2015, IEEE International Symposium on Circuits and Systems, ISCAS 2015. IEEE, p. 1346-1349

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  8. Published

    Object sorting using a distributed manipulator array

    Walsh, D. & Dudek, P., 2014, 14th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2014. IEEE

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  9. Published

    A new method for fast skeletonization of binary images on cellular processor arrays

    Wang, B., Mroszczyk, P. & Dudek, P., 2014, 14th International Workshop on Cellular Nanoscale Networks and their Applications, CNNA 2014. IEEE

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  10. Published

    Coarse grain mapping method for image processing on fine grain cellular processor arrays

    Wang, B. & Dudek, P., 2012, International Workshop on Cellular Nanoscale Networks and their Applications|Int. Workshop Cell. Nanoscale Netw. Appl..

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

Research Explorer downloads

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Research output: Contribution to journalArticle

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Research output: Chapter in Book/Report/Conference proceedingConference contribution