Dr Dirk Koch

Lecturer

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Publications

  1. 2019
  2. Accepted/In press

    Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures

    Vaishnav, A., Pham, K. & Koch, D., 4 May 2019, (Accepted/In press) 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  3. Accepted/In press

    Scalable Filtering Modules for Database Acceleration on FPGAs

    Manev, K., Vaishnav, A., Kritikakis, C. & Koch, D., 4 May 2019, (Accepted/In press) 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  4. Accepted/In press

    EFCAD – an Embedded FPGA CAD Tool Flow For Enabling On-Chip Self-Compilation

    Pham, K., Vesper, M., Koch, D. & Hung, E., 4 Mar 2019, (Accepted/In press) The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  5. 2018
  6. Accepted/In press

    Live Migration for OpenCL FPGA Accelerators

    Vaishnav, A., Pham, K. & Koch, D., 17 Sep 2018, (Accepted/In press) International Conference on Field-Programmable Technology (FPT). Naha, Okinawa, Japan: IEEE Xplore, 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  7. Accepted/In press

    Large Utility Sorting on FPGAs

    Manev, K. & Koch, D., 16 Sep 2018, (Accepted/In press).

    Research output: Contribution to conferencePaper

  8. Accepted/In press

    A Survey on FPGA Virtualization

    Vaishnav, A., Pham, K. & Koch, D., 21 May 2018, (Accepted/In press) 28th International Conference on Field Programmable Logic and Application (FPL). Dublin, Ireland, 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  9. Accepted/In press

    Resource Elastic Virtualization for FPGAs using OpenCL

    Vaishnav, A., Pham, K., Koch, D. & Garside, J., 21 May 2018, (Accepted/In press) 28th International Conference on Field Programmable Logic and Application (FPL). Dublin, Ireland, 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  10. Published

    A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine

    Garcia Ordaz, J. R. & Koch, D., 2018, The 29th IEEE International Conference on Application-specific Systems, Architectures and Processors 2018.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  11. Published

    HLS Enabled Partially Reconfigurable Module Implementation

    Grigore, B., Koch, D. & Kritikakis, C., 2018, ARCS 2018. 12 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  12. Published

    IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs

    Pham, K., Horta, E., Koch, D., Vaishnav, A. & Kuhn, T., 2018, IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Research output: Chapter in Book/Report/Conference proceedingConference contribution