Prof Anthony Goodacre

Professor of Computer Architectures

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Publications

  1. 2020
  2. Published

    FastPath_MP: Low Overhead & Energy Efficient FPGA-based Storage Multi-Paths

    Stratikopoulos, A., Kotselidis, C., Goodacre, J. & Luján, M., 26 Nov 2020, In: ACM Transactions on Architecture and Code Optimization. 17, 4, 37.

    Research output: Contribution to journalArticlepeer-review

  3. Accepted/In press

    On the Routing and Scalability of MZI-based Optical Beneš Interconnects

    Kynigos, M., Pascual Saiz, J., Navaridas, J., Luján, M. & Goodacre, J., 10 Oct 2020, (Accepted/In press) In: Nano Communication Networks.

    Research output: Contribution to journalArticlepeer-review

  4. Published

    3D Interconected Die Stack

    Goodacre, A., 13 May 2020, Patent No. GB2565310A, 8 Aug 2017

    Research output: Patent

  5. Published

    Toward FPGA-Based HPC: Advancing Interconnect Technologies

    Lant, J., Navaridas, J., Luján, M. & Goodacre, J., 1 Jan 2020, In: IEEE Micro. 40, 1, p. 25-34 10.1109/MM.2019.2950655.

    Research output: Contribution to journalArticlepeer-review

  6. Published
  7. 2019
  8. Published

    Scalability analysis of optical Beneš networks based on thermally/electrically tuned Mach-Zehnder interferometers

    Kynigos, M., Pascual Saiz, J., Navaridas, J., Luján, M. & Goodacre, J., 13 Oct 2019, NoCArc: Proceedings of the 12th International Workshop on Network on Chip Architectures. Association for Computing Machinery, p. 1-6 6 p. 9

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  9. Published

    Scaling the Capacity of Memory Systems; Evolution and Key Approaches

    Paraskevas, K., Attwood, A., Luján, M. & Goodacre, J., 1 Oct 2019, Proceedings of the International Symposium on Memory Systems, MEMSYS 2019. Washington, District of Columbia — September 30 - October 03, 2019: Association for Computing Machinery, 15 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  10. Published

    Design Exploration of Multi-tier interconnects for Exascale systems

    Navaridas, J., Lant, J., Pascual Saiz, J., Luján, M. & Goodacre, J., 5 Aug 2019, ICPP 2019 : International Conference on Parallel Processing .

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  11. Accepted/In press

    Receive-Side Notification for Enhanced RDMA in FPGA Based Networks

    Lant, J., Attwood, A., Navaridas, J., Luján, M. & Goodacre, J., 14 Feb 2019, (Accepted/In press) International Conference on Architecture of Computing Systems.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  12. 2018
  13. Published

    Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development

    Katevenis, M., Ammendola, R., Biagioni, A., Cretaro, P., Frezza, O., Lo Cicero, F., Lonardo, A., Martinelli, M., Paolucci, P. S., Pastorelli, E., Simula, F., Vicini, P., Taffoni, G., Pascual, J. A., Navaridas, J., Luján, M., Goodacre, J., Lietzow, B., Mouzakitis, A., Chrysos, N. & 8 others, Marazakis, M., Gorlani, P., Cozzini, S., Brandino, G. P., Koutsourakis, P., Ruth, J. V., Zhang, Y. & Kersten, M., 1 Sep 2018, In: Microprocessors and Microsystems. 61, p. 58-71 14 p.

    Research output: Contribution to journalArticlepeer-review

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Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review