Understanding the interconnection network of SpiNNakerCitation formats

Standard

Understanding the interconnection network of SpiNNaker. / Navaridas, Javier; Luján, Mikel; Miguel-Alonso, Jose; Plana, Luis A.; Furber, Steve.

Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing. Association for Computing Machinery, 2009. p. 286-295.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Navaridas, J, Luján, M, Miguel-Alonso, J, Plana, LA & Furber, S 2009, Understanding the interconnection network of SpiNNaker. in Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing. Association for Computing Machinery, pp. 286-295, 23rd International Conference on Supercomputing, ICS'09, Yorktown Heights, NY, 1/07/09. https://doi.org/10.1145/1542275.1542317

APA

Navaridas, J., Luján, M., Miguel-Alonso, J., Plana, L. A., & Furber, S. (2009). Understanding the interconnection network of SpiNNaker. In Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing (pp. 286-295). Association for Computing Machinery. https://doi.org/10.1145/1542275.1542317

Vancouver

Navaridas J, Luján M, Miguel-Alonso J, Plana LA, Furber S. Understanding the interconnection network of SpiNNaker. In Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing. Association for Computing Machinery. 2009. p. 286-295 https://doi.org/10.1145/1542275.1542317

Author

Navaridas, Javier ; Luján, Mikel ; Miguel-Alonso, Jose ; Plana, Luis A. ; Furber, Steve. / Understanding the interconnection network of SpiNNaker. Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing. Association for Computing Machinery, 2009. pp. 286-295

Bibtex

@inproceedings{bcab95d22d6e4e9b8636d18abfd1b5a3,
title = "Understanding the interconnection network of SpiNNaker",
abstract = "SpiNNaker is a massively parallel architecture designed to model large-scale spiking neural networks in (biological) real-time. Its design is based around ad-hoc multi-core System-on-Chips which are interconnected using a two-dimensional toroidal triangular mesh. Neurons are modeled in software and their spikes generate packets that propagate through the on- and inter-chip communication fabric relying on custom-made on-chip multicast routers. This paper models and evaluates large-scale instances of its novel interconnect (more than 65 thousand nodes, or over one million computing cores), focusing on real-time features and fault-tolerance. The key contribution can be summarized as understanding the properties of the feasible topologies and establishing the stable operation of the SpiNNaker under different levels of degradation. First we derive analytically the topological characteristics of the network, which are later confirmed by experimental work. With the computational model developed, we investigate the topology of SpiNNaker, and compare it with a standard 3-dimensional torus. The novel emergency routing mechanism, implemented within the routers, allows the topology of SpiNNaker to be more robust than the 3-dimensional torus, regardless of the latter having better topological characteristics. Furthermore, we obtain optimal values of two router parameters related with livelock and deadlock avoidance mechanisms. Copyright 2009 ACM.",
keywords = "Analytical evaluation, Biologically inspired architecture, Fault tolerance, Interconnection networks, Massively parallel architecture, Performance evaluation, Real-time applications, Spiking neurons, Systems on chip",
author = "Javier Navaridas and Mikel Luj{\'a}n and Jose Miguel-Alonso and Plana, {Luis A.} and Steve Furber",
year = "2009",
doi = "10.1145/1542275.1542317",
language = "English",
isbn = "9781605584980",
pages = "286--295",
booktitle = "Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing",
publisher = "Association for Computing Machinery",
address = "United States",
note = "23rd International Conference on Supercomputing, ICS'09 ; Conference date: 01-07-2009",
url = "http://dblp.uni-trier.de/db/conf/ics/ics2009.html#NavaridasLMPF09http://dblp.uni-trier.de/rec/bibtex/conf/ics/NavaridasLMPF09.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/ics/NavaridasLMPF09",

}

RIS

TY - GEN

T1 - Understanding the interconnection network of SpiNNaker

AU - Navaridas, Javier

AU - Luján, Mikel

AU - Miguel-Alonso, Jose

AU - Plana, Luis A.

AU - Furber, Steve

PY - 2009

Y1 - 2009

N2 - SpiNNaker is a massively parallel architecture designed to model large-scale spiking neural networks in (biological) real-time. Its design is based around ad-hoc multi-core System-on-Chips which are interconnected using a two-dimensional toroidal triangular mesh. Neurons are modeled in software and their spikes generate packets that propagate through the on- and inter-chip communication fabric relying on custom-made on-chip multicast routers. This paper models and evaluates large-scale instances of its novel interconnect (more than 65 thousand nodes, or over one million computing cores), focusing on real-time features and fault-tolerance. The key contribution can be summarized as understanding the properties of the feasible topologies and establishing the stable operation of the SpiNNaker under different levels of degradation. First we derive analytically the topological characteristics of the network, which are later confirmed by experimental work. With the computational model developed, we investigate the topology of SpiNNaker, and compare it with a standard 3-dimensional torus. The novel emergency routing mechanism, implemented within the routers, allows the topology of SpiNNaker to be more robust than the 3-dimensional torus, regardless of the latter having better topological characteristics. Furthermore, we obtain optimal values of two router parameters related with livelock and deadlock avoidance mechanisms. Copyright 2009 ACM.

AB - SpiNNaker is a massively parallel architecture designed to model large-scale spiking neural networks in (biological) real-time. Its design is based around ad-hoc multi-core System-on-Chips which are interconnected using a two-dimensional toroidal triangular mesh. Neurons are modeled in software and their spikes generate packets that propagate through the on- and inter-chip communication fabric relying on custom-made on-chip multicast routers. This paper models and evaluates large-scale instances of its novel interconnect (more than 65 thousand nodes, or over one million computing cores), focusing on real-time features and fault-tolerance. The key contribution can be summarized as understanding the properties of the feasible topologies and establishing the stable operation of the SpiNNaker under different levels of degradation. First we derive analytically the topological characteristics of the network, which are later confirmed by experimental work. With the computational model developed, we investigate the topology of SpiNNaker, and compare it with a standard 3-dimensional torus. The novel emergency routing mechanism, implemented within the routers, allows the topology of SpiNNaker to be more robust than the 3-dimensional torus, regardless of the latter having better topological characteristics. Furthermore, we obtain optimal values of two router parameters related with livelock and deadlock avoidance mechanisms. Copyright 2009 ACM.

KW - Analytical evaluation

KW - Biologically inspired architecture

KW - Fault tolerance

KW - Interconnection networks

KW - Massively parallel architecture

KW - Performance evaluation

KW - Real-time applications

KW - Spiking neurons

KW - Systems on chip

U2 - 10.1145/1542275.1542317

DO - 10.1145/1542275.1542317

M3 - Conference contribution

SN - 9781605584980

SP - 286

EP - 295

BT - Proceedings of the International Conference on Supercomputing|Proc Int Conf Supercomputing

PB - Association for Computing Machinery

T2 - 23rd International Conference on Supercomputing, ICS'09

Y2 - 1 July 2009

ER -