Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated SystemsCitation formats

TY - GEN

T1 - Ultra-Low Swing CMOS Transceiver for 2.5-D Integrated Systems

AU - Mroszczyk, Przemyslaw

AU - Pavlidis, Vasileios

PY - 2018

Y1 - 2018

N2 - This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4× higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.

AB - This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4× higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.

KW - 2.5-D integration

KW - I/O design

KW - Low swing

KW - digital trimming

KW - mismatch cancellation

KW - passive interposer

UR - http://www.scopus.com/inward/record.url?scp=85047911945&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2018.8357298

DO - 10.1109/ISQED.2018.8357298

M3 - Conference contribution

SN - 9781538612149

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 262

EP - 267

BT - 2018 19th International Symposium on Quality Electronic Design, ISQED 2018

ER -