Type Information Elimination from Objects on Architectures with Tagged Pointers SupportCitation formats

Standard

Type Information Elimination from Objects on Architectures with Tagged Pointers Support. / Rodchenko, Andrey; Kotselidis, Christos; Nisbet, Andy; Pop, Antoniu; Luján, Mikel.

In: IEEE Transactions on Computers, Vol. 67, No. 1, 29.06.2017, p. 130-143.

Research output: Contribution to journalArticlepeer-review

Harvard

Rodchenko, A, Kotselidis, C, Nisbet, A, Pop, A & Luján, M 2017, 'Type Information Elimination from Objects on Architectures with Tagged Pointers Support', IEEE Transactions on Computers, vol. 67, no. 1, pp. 130-143. https://doi.org/10.1109/TC.2017.2709739

APA

Vancouver

Author

Rodchenko, Andrey ; Kotselidis, Christos ; Nisbet, Andy ; Pop, Antoniu ; Luján, Mikel. / Type Information Elimination from Objects on Architectures with Tagged Pointers Support. In: IEEE Transactions on Computers. 2017 ; Vol. 67, No. 1. pp. 130-143.

Bibtex

@article{308317b41b03454c8eee2e5db7b4c641,
title = "Type Information Elimination from Objects on Architectures with Tagged Pointers Support",
abstract = "Implementations of object-oriented programming languages associate type information with each object to perform various runtime tasks such as dynamic dispatch, type introspection, and reflection. A common means of storing such relation is by inserting a pointer to the associated type information into every object. Such an approach, however, introduces memory and performance overheads when compared with non-object-oriented languages. Recent 64-bit computer architectures have added support for tagged pointers by ignoring a number of bits – tag – of memory addresses during memory access operations and utilize them for other purposes; mainly security. This paper presents the first investigation into how this hardware support can be exploited by a Java Virtual Machine to remove type information from objects. Moreover, we propose novel hardware extensions to the address generation and load-store units to achieve low-overhead type information retrieval and tagged object pointers compression-decompression. The evaluation has been conducted after integrating the Maxine VM and the ZSim microarchitectural simulator. The results, across all the DaCapo benchmark suite, pseudo-SPECjbb2005, SLAMBench and GraphChi-PR executed to completion, show up to 26% and10% geometric mean heap space savings, up to 50% and 12% geometric mean dynamic DRAM energy reduction, and up to 49% and 3% geometric mean execution time reduction with no significant performance regressions.",
keywords = "Runtime environments, high-level language architectures, simulation.",
author = "Andrey Rodchenko and Christos Kotselidis and Andy Nisbet and Antoniu Pop and Mikel Luj{\'a}n",
year = "2017",
month = jun,
day = "29",
doi = "10.1109/TC.2017.2709739",
language = "English",
volume = "67",
pages = "130--143",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society ",
number = "1",

}

RIS

TY - JOUR

T1 - Type Information Elimination from Objects on Architectures with Tagged Pointers Support

AU - Rodchenko, Andrey

AU - Kotselidis, Christos

AU - Nisbet, Andy

AU - Pop, Antoniu

AU - Luján, Mikel

PY - 2017/6/29

Y1 - 2017/6/29

N2 - Implementations of object-oriented programming languages associate type information with each object to perform various runtime tasks such as dynamic dispatch, type introspection, and reflection. A common means of storing such relation is by inserting a pointer to the associated type information into every object. Such an approach, however, introduces memory and performance overheads when compared with non-object-oriented languages. Recent 64-bit computer architectures have added support for tagged pointers by ignoring a number of bits – tag – of memory addresses during memory access operations and utilize them for other purposes; mainly security. This paper presents the first investigation into how this hardware support can be exploited by a Java Virtual Machine to remove type information from objects. Moreover, we propose novel hardware extensions to the address generation and load-store units to achieve low-overhead type information retrieval and tagged object pointers compression-decompression. The evaluation has been conducted after integrating the Maxine VM and the ZSim microarchitectural simulator. The results, across all the DaCapo benchmark suite, pseudo-SPECjbb2005, SLAMBench and GraphChi-PR executed to completion, show up to 26% and10% geometric mean heap space savings, up to 50% and 12% geometric mean dynamic DRAM energy reduction, and up to 49% and 3% geometric mean execution time reduction with no significant performance regressions.

AB - Implementations of object-oriented programming languages associate type information with each object to perform various runtime tasks such as dynamic dispatch, type introspection, and reflection. A common means of storing such relation is by inserting a pointer to the associated type information into every object. Such an approach, however, introduces memory and performance overheads when compared with non-object-oriented languages. Recent 64-bit computer architectures have added support for tagged pointers by ignoring a number of bits – tag – of memory addresses during memory access operations and utilize them for other purposes; mainly security. This paper presents the first investigation into how this hardware support can be exploited by a Java Virtual Machine to remove type information from objects. Moreover, we propose novel hardware extensions to the address generation and load-store units to achieve low-overhead type information retrieval and tagged object pointers compression-decompression. The evaluation has been conducted after integrating the Maxine VM and the ZSim microarchitectural simulator. The results, across all the DaCapo benchmark suite, pseudo-SPECjbb2005, SLAMBench and GraphChi-PR executed to completion, show up to 26% and10% geometric mean heap space savings, up to 50% and 12% geometric mean dynamic DRAM energy reduction, and up to 49% and 3% geometric mean execution time reduction with no significant performance regressions.

KW - Runtime environments, high-level language architectures, simulation.

U2 - 10.1109/TC.2017.2709739

DO - 10.1109/TC.2017.2709739

M3 - Article

VL - 67

SP - 130

EP - 143

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 1

ER -