The design of an asynchronous VHDL synthesizer
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
Abstract
This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on 'micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit. © 1998 IEEE.
Bibliographical metadata
Original language | English |
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Title of host publication | Proceedings -Design, Automation and Test in Europe, DATE|Proc. Des. Autom. Test Eur. DATE |
Publisher | IEEE Computer Society |
Pages | 44-51 |
Number of pages | 7 |
DOIs | |
Publication status | Published - 1998 |
Event | Design, Automation and Test in Europe, DATE 1998 - Paris Event duration: 1 Jul 1998 → … http://dblp.uni-trier.de/db/conf/date/date1998.html#TanFY98http://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98 |
Conference
Conference | Design, Automation and Test in Europe, DATE 1998 |
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City | Paris |
Period | 1/07/98 → … |
Internet address |