The design of an asynchronous VHDL synthesizer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on 'micropipelines', a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit. © 1998 IEEE.

Bibliographical metadata

Original languageEnglish
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE|Proc. Des. Autom. Test Eur. DATE
PublisherIEEE Computer Society
Pages44-51
Number of pages7
DOIs
Publication statusPublished - 1998
EventDesign, Automation and Test in Europe, DATE 1998 - Paris
Event duration: 1 Jul 1998 → …
http://dblp.uni-trier.de/db/conf/date/date1998.html#TanFY98http://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/date/TanFY98

Conference

ConferenceDesign, Automation and Test in Europe, DATE 1998
CityParis
Period1/07/98 → …
Internet address