SpiNNaker: Design and implementation of a GALS multicore system-on-chipCitation formats

  • External authors:
  • David Clark
  • Simon Davidson
  • Eustace Painkras
  • Jeffrey Pepper
  • Steve Temple
  • John Bainbridge

Standard

SpiNNaker: Design and implementation of a GALS multicore system-on-chip. / Plana, Luis A.; Clark, David; Davidson, Simon; Furber, Steve; Garside, Jim; Painkras, Eustace; Pepper, Jeffrey; Temple, Steve; Bainbridge, John.

In: ACM Journal on Emerging Technologies in Computing Systems, Vol. 7, No. 4, 17, 12.2011.

Research output: Contribution to journalArticlepeer-review

Harvard

Plana, LA, Clark, D, Davidson, S, Furber, S, Garside, J, Painkras, E, Pepper, J, Temple, S & Bainbridge, J 2011, 'SpiNNaker: Design and implementation of a GALS multicore system-on-chip', ACM Journal on Emerging Technologies in Computing Systems, vol. 7, no. 4, 17. https://doi.org/10.1145/2043643.2043647

APA

Plana, L. A., Clark, D., Davidson, S., Furber, S., Garside, J., Painkras, E., Pepper, J., Temple, S., & Bainbridge, J. (2011). SpiNNaker: Design and implementation of a GALS multicore system-on-chip. ACM Journal on Emerging Technologies in Computing Systems, 7(4), [17]. https://doi.org/10.1145/2043643.2043647

Vancouver

Plana LA, Clark D, Davidson S, Furber S, Garside J, Painkras E et al. SpiNNaker: Design and implementation of a GALS multicore system-on-chip. ACM Journal on Emerging Technologies in Computing Systems. 2011 Dec;7(4). 17. https://doi.org/10.1145/2043643.2043647

Author

Plana, Luis A. ; Clark, David ; Davidson, Simon ; Furber, Steve ; Garside, Jim ; Painkras, Eustace ; Pepper, Jeffrey ; Temple, Steve ; Bainbridge, John. / SpiNNaker: Design and implementation of a GALS multicore system-on-chip. In: ACM Journal on Emerging Technologies in Computing Systems. 2011 ; Vol. 7, No. 4.

Bibtex

@article{1364dd639dfa48d9ad009e4e62535eeb,
title = "SpiNNaker: Design and implementation of a GALS multicore system-on-chip",
abstract = "The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately,most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met. {\textcopyright} 2011.",
keywords = "Asynchronous system, Computer-aided design, Globally-asynchronous locallysynchronous system, Intellectual property, Network-on-chip",
author = "Plana, {Luis A.} and David Clark and Simon Davidson and Steve Furber and Jim Garside and Eustace Painkras and Jeffrey Pepper and Steve Temple and John Bainbridge",
year = "2011",
month = dec,
doi = "10.1145/2043643.2043647",
language = "English",
volume = "7",
journal = "ACM Journal on Emerging Technologies in Computing Systems",
issn = "1550-4832",
publisher = "ACM Special Interest Group",
number = "4",

}

RIS

TY - JOUR

T1 - SpiNNaker: Design and implementation of a GALS multicore system-on-chip

AU - Plana, Luis A.

AU - Clark, David

AU - Davidson, Simon

AU - Furber, Steve

AU - Garside, Jim

AU - Painkras, Eustace

AU - Pepper, Jeffrey

AU - Temple, Steve

AU - Bainbridge, John

PY - 2011/12

Y1 - 2011/12

N2 - The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately,most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met. © 2011.

AB - The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately,most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met. © 2011.

KW - Asynchronous system

KW - Computer-aided design

KW - Globally-asynchronous locallysynchronous system

KW - Intellectual property

KW - Network-on-chip

U2 - 10.1145/2043643.2043647

DO - 10.1145/2043643.2043647

M3 - Article

VL - 7

JO - ACM Journal on Emerging Technologies in Computing Systems

JF - ACM Journal on Emerging Technologies in Computing Systems

SN - 1550-4832

IS - 4

M1 - 17

ER -