Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As the silicon industry moves into deep nanoscale technologies, preserving Mean Time to Failure at acceptable levels becomes a first-order challenge. The operational stress, along with the inefficient power dissipation and the unsustainable thermal thresholds increase the wear-induced failures. As a result, faster wear-out leads to earlier performance degradation with eventual device breakdown. Furthermore, the proliferation of asymmetric multicores is tightly coupled with an increasing susceptibility to variable wear-out rate within the components of processors. This paper investigates the reliability boundaries of asymmetric multicores, which span from embedded systems to high performance computing domains, by performing a continuous- operation reliability assessment. As our experimental analysis illustrates, the variation between the least and the most aged hardware resource equals to 2.6 years. Motivated by this finding, we show that an MTTF-aware, asymmetric configuration prolongs its lifetime by 21%.

Bibliographical metadata

Original languageEnglish
Title of host publication32nd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
PublisherIEEE
Publication statusAccepted/In press - 22 Jul 2019