Scan testing of asynchronous sequential circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A method to design and test asynchronous sequential circuits (ASCs) based on the micropipeline design style is presented in this paper. According to the proposed scan test approach the combinational block is tested separately by scanning the test vectors in and shifting the responses out of the state registers. This provides for the detection of all single stuck-at and delay faults in the ASC under test. The complexity of the test procedure of such a testable ASC is reduced to that of the combinational circuit. Tests for the combinational circuit and state holding elements can be derived using standard test generation techniques.

Bibliographical metadata

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI|Proc IEEE Great Lakes Symp VLSI
Place of PublicationLos Alamitos, CA, United States
PublisherIEEE
Pages224-229
Number of pages5
Publication statusPublished - 1995
EventProceedings of the 5th Great Lakes Symposium on VLSI - Buffalo, NY, USA
Event duration: 1 Jul 1995 → …
http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1995.html#PetlinF95http://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/PetlinF95.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/glvlsi/PetlinF95

Conference

ConferenceProceedings of the 5th Great Lakes Symposium on VLSI
CityBuffalo, NY, USA
Period1/07/95 → …
Internet address