Scalable communications for a million-core neural processing architecture

Research output: Contribution to journalArticlepeer-review

  • External authors:
  • Cameron Patterson
  • Eustace Painkras
  • Steve Temple
  • Javier Navaridas
  • Thomas Sharp

Abstract

The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker's hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system. © 2012 Elsevier Inc. All rights reserved.

Bibliographical metadata

Original languageEnglish
Pages (from-to)1507-1520
Number of pages13
JournalJournal of Parallel and Distributed Computing
Volume72
Issue number11
DOIs
Publication statusPublished - Nov 2012