Rapid Overlay Builder for Xilinx FPGACitation formats

  • Authors:
  • Dirk Koch
  • Leslay Shannon (Editor)
  • David Andrews (Editor)

Standard

Rapid Overlay Builder for Xilinx FPGA. / Koch, Dirk; Shannon, Leslay (Editor); Andrews, David (Editor).

Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. ed. / Leslay Shannon; David Andrews. Vol. 23 IEEE Computer Society , 2015. p. 17-20.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Koch, D, Shannon, L (ed.) & Andrews, D (ed.) 2015, Rapid Overlay Builder for Xilinx FPGA. in L Shannon & D Andrews (eds), Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. vol. 23, IEEE Computer Society , pp. 17-20, 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, 2/05/15. https://doi.org/10.1109/FCCM.2015.48

APA

Koch, D., Shannon, L. (Ed.), & Andrews, D. (Ed.) (2015). Rapid Overlay Builder for Xilinx FPGA. In L. Shannon, & D. Andrews (Eds.), Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015 (Vol. 23, pp. 17-20). IEEE Computer Society . https://doi.org/10.1109/FCCM.2015.48

Vancouver

Koch D, Shannon L, (ed.), Andrews D, (ed.). Rapid Overlay Builder for Xilinx FPGA. In Shannon L, Andrews D, editors, Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. Vol. 23. IEEE Computer Society . 2015. p. 17-20 https://doi.org/10.1109/FCCM.2015.48

Author

Koch, Dirk ; Shannon, Leslay (Editor) ; Andrews, David (Editor). / Rapid Overlay Builder for Xilinx FPGA. Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015. editor / Leslay Shannon ; David Andrews. Vol. 23 IEEE Computer Society , 2015. pp. 17-20

Bibtex

@inproceedings{26f8e6ce25894408a0d125d9d4e6e2f9,
title = "Rapid Overlay Builder for Xilinx FPGA",
abstract = "Overlays are emerging as useful design patterns for solving reconfigurable computing problems. Overlays consist of compiler-like tools and an architecture written in RTL, making it easier for users to quickly compile high-level languages into FPGAs. Despite a high degree of regularity and repetition present in most overlays, it takes a long time for FPGA tools to generate the configuration bit stream. This paper proposes a methodology called Rapid Overlay Builder, or ROB, that combines module relocation, module variants and an efficient form of {"}router less{"} module stitching that we call zipping. Our case study demonstrates up to 22 times speedup in compile-time over a regular Xilinx ISE compilation, while achieving higher clock speeds. By applying ROB, we anticipate that overlays can be implemented more quickly and with more consistent clock rates.",
keywords = "FPGA, Overlay",
author = "Dirk Koch and Leslay Shannon and David Andrews",
year = "2015",
month = may,
day = "2",
doi = "10.1109/FCCM.2015.48",
language = "English",
isbn = "978-1-4799-9969-9",
volume = "23",
pages = "17--20",
editor = "Leslay Shannon and David Andrews",
booktitle = "Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015",
publisher = "IEEE Computer Society ",
address = "United States",
note = "23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015 ; Conference date: 02-05-2015 Through 06-05-2015",
url = "http://fccm.org",

}

RIS

TY - GEN

T1 - Rapid Overlay Builder for Xilinx FPGA

AU - Koch, Dirk

A2 - Shannon, Leslay

A2 - Andrews, David

A2 - Shannon, Leslay

A2 - Andrews, David

PY - 2015/5/2

Y1 - 2015/5/2

N2 - Overlays are emerging as useful design patterns for solving reconfigurable computing problems. Overlays consist of compiler-like tools and an architecture written in RTL, making it easier for users to quickly compile high-level languages into FPGAs. Despite a high degree of regularity and repetition present in most overlays, it takes a long time for FPGA tools to generate the configuration bit stream. This paper proposes a methodology called Rapid Overlay Builder, or ROB, that combines module relocation, module variants and an efficient form of "router less" module stitching that we call zipping. Our case study demonstrates up to 22 times speedup in compile-time over a regular Xilinx ISE compilation, while achieving higher clock speeds. By applying ROB, we anticipate that overlays can be implemented more quickly and with more consistent clock rates.

AB - Overlays are emerging as useful design patterns for solving reconfigurable computing problems. Overlays consist of compiler-like tools and an architecture written in RTL, making it easier for users to quickly compile high-level languages into FPGAs. Despite a high degree of regularity and repetition present in most overlays, it takes a long time for FPGA tools to generate the configuration bit stream. This paper proposes a methodology called Rapid Overlay Builder, or ROB, that combines module relocation, module variants and an efficient form of "router less" module stitching that we call zipping. Our case study demonstrates up to 22 times speedup in compile-time over a regular Xilinx ISE compilation, while achieving higher clock speeds. By applying ROB, we anticipate that overlays can be implemented more quickly and with more consistent clock rates.

KW - FPGA

KW - Overlay

U2 - 10.1109/FCCM.2015.48

DO - 10.1109/FCCM.2015.48

M3 - Conference contribution

SN - 978-1-4799-9969-9

VL - 23

SP - 17

EP - 20

BT - Prooceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015

PB - IEEE Computer Society

T2 - 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015

Y2 - 2 May 2015 through 6 May 2015

ER -