Rapid Overlay Builder for Xilinx FPGA

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Authors:
  • Dirk Koch
  • Leslay Shannon (Editor)
  • David Andrews (Editor)

Abstract

Overlays are emerging as useful design patterns for solving reconfigurable computing problems. Overlays consist of compiler-like tools and an architecture written in RTL, making it easier for users to quickly compile high-level languages into FPGAs. Despite a high degree of regularity and repetition present in most overlays, it takes a long time for FPGA tools to generate the configuration bit stream. This paper proposes a methodology called Rapid Overlay Builder, or ROB, that combines module relocation, module variants and an efficient form of "router less" module stitching that we call zipping. Our case study demonstrates up to 22 times speedup in compile-time over a regular Xilinx ISE compilation, while achieving higher clock speeds. By applying ROB, we anticipate that overlays can be implemented more quickly and with more consistent clock rates.

Bibliographical metadata

Original languageEnglish
Title of host publicationProoceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
EditorsLeslay Shannon, David Andrews
PublisherIEEE Computer Society
Pages17-20
Number of pages4
Volume23
ISBN (Print)978-1-4799-9969-9
DOIs
Publication statusPublished - 2 May 2015
Event23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015 - Vancouver, BC, Canada
Event duration: 2 May 20156 May 2015
http://fccm.org

Conference

Conference23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
CityVancouver, BC, Canada
Period2/05/156/05/15
Internet address