PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAsCitation formats

Standard

PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs. / Maragos, Kostas; Lentaris, George; Soudris, Dimitrios; Pavlidis, Vasileios.

2018. Poster session presented at International Symposium on Field-Programmable Gate Arrays, United States.

Research output: Contribution to conferencePosterpeer-review

Harvard

Maragos, K, Lentaris, G, Soudris, D & Pavlidis, V 2018, 'PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs', International Symposium on Field-Programmable Gate Arrays, United States, 24/02/19 - 26/02/19.

APA

Maragos, K., Lentaris, G., Soudris, D., & Pavlidis, V. (Accepted/In press). PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs. Poster session presented at International Symposium on Field-Programmable Gate Arrays, United States.

Vancouver

Maragos K, Lentaris G, Soudris D, Pavlidis V. PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs. 2018. Poster session presented at International Symposium on Field-Programmable Gate Arrays, United States.

Author

Maragos, Kostas ; Lentaris, George ; Soudris, Dimitrios ; Pavlidis, Vasileios. / PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs. Poster session presented at International Symposium on Field-Programmable Gate Arrays, United States.

Bibtex

@conference{b3fc87f7a9cb46e89c8a0625c95619b5,
title = "PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs",
abstract = "In this work we introduce a method to improve the energy efficiency of the FPGA devices by reducing the pessimistic operation guardbands posed by the commercial EDA tools. The proposed method bases on a voltage scaling scheme that reliably decreases the supply voltage. We deploy a uniform network of delay-based sensors across the fabric of the FPGA to sense all process, voltage and temperature variation (PVT) effects. The delay of all the sensors is calibrated to match the worst critical path delay of the target application. In that respect, the monitoring of the sensor network enables the indirect assessment of the functional integrity of the target application. The distributed placement of the sensors provides the desired sensitivity with appropriate granularity across the fabric and allows us to consider the worst-case scenario. The sensor network is integrated during the development cycle as a ready-to-use software IP with negligible resource overhead, for example, 1-2% of a Zynq XC7Z020 FPGA for 10 sensors. The sensitivity of the sensors to all PVT variations and the correlation with the application operation is verified through extensive testing by using multiple FPGAs and realistic benchmarks. The aforementioned approach facilitates a closed-loop voltage scaling scheme to regulate the supply voltage and reduce the power of the system. In our experiments on a set of 28nm Xilinx XC7Z020 SoC FPGAs and realistic digital signal processing (DSP) benchmarks, we demonstrate up to 27.2% decrease in power for 13% decrease in voltage, while retaining the nominal timing performance.",
author = "Kostas Maragos and George Lentaris and Dimitrios Soudris and Vasileios Pavlidis",
year = "2018",
month = nov,
day = "15",
language = "English",
note = "International Symposium on Field-Programmable Gate Arrays ; Conference date: 24-02-2019 Through 26-02-2019",
url = "http://isfpga.org/",

}

RIS

TY - CONF

T1 - PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs

AU - Maragos, Kostas

AU - Lentaris, George

AU - Soudris, Dimitrios

AU - Pavlidis, Vasileios

PY - 2018/11/15

Y1 - 2018/11/15

N2 - In this work we introduce a method to improve the energy efficiency of the FPGA devices by reducing the pessimistic operation guardbands posed by the commercial EDA tools. The proposed method bases on a voltage scaling scheme that reliably decreases the supply voltage. We deploy a uniform network of delay-based sensors across the fabric of the FPGA to sense all process, voltage and temperature variation (PVT) effects. The delay of all the sensors is calibrated to match the worst critical path delay of the target application. In that respect, the monitoring of the sensor network enables the indirect assessment of the functional integrity of the target application. The distributed placement of the sensors provides the desired sensitivity with appropriate granularity across the fabric and allows us to consider the worst-case scenario. The sensor network is integrated during the development cycle as a ready-to-use software IP with negligible resource overhead, for example, 1-2% of a Zynq XC7Z020 FPGA for 10 sensors. The sensitivity of the sensors to all PVT variations and the correlation with the application operation is verified through extensive testing by using multiple FPGAs and realistic benchmarks. The aforementioned approach facilitates a closed-loop voltage scaling scheme to regulate the supply voltage and reduce the power of the system. In our experiments on a set of 28nm Xilinx XC7Z020 SoC FPGAs and realistic digital signal processing (DSP) benchmarks, we demonstrate up to 27.2% decrease in power for 13% decrease in voltage, while retaining the nominal timing performance.

AB - In this work we introduce a method to improve the energy efficiency of the FPGA devices by reducing the pessimistic operation guardbands posed by the commercial EDA tools. The proposed method bases on a voltage scaling scheme that reliably decreases the supply voltage. We deploy a uniform network of delay-based sensors across the fabric of the FPGA to sense all process, voltage and temperature variation (PVT) effects. The delay of all the sensors is calibrated to match the worst critical path delay of the target application. In that respect, the monitoring of the sensor network enables the indirect assessment of the functional integrity of the target application. The distributed placement of the sensors provides the desired sensitivity with appropriate granularity across the fabric and allows us to consider the worst-case scenario. The sensor network is integrated during the development cycle as a ready-to-use software IP with negligible resource overhead, for example, 1-2% of a Zynq XC7Z020 FPGA for 10 sensors. The sensitivity of the sensors to all PVT variations and the correlation with the application operation is verified through extensive testing by using multiple FPGAs and realistic benchmarks. The aforementioned approach facilitates a closed-loop voltage scaling scheme to regulate the supply voltage and reduce the power of the system. In our experiments on a set of 28nm Xilinx XC7Z020 SoC FPGAs and realistic digital signal processing (DSP) benchmarks, we demonstrate up to 27.2% decrease in power for 13% decrease in voltage, while retaining the nominal timing performance.

M3 - Poster

T2 - International Symposium on Field-Programmable Gate Arrays

Y2 - 24 February 2019 through 26 February 2019

ER -