Portable module relocation and bitstream compression for Xilinx FPGAsCitation formats

  • Authors:
  • Dirk Koch
  • Andreas Herkersdorf (Editor)
  • Norbert Wehn (Editor)
  • Michael Hubner (Editor)

Standard

Portable module relocation and bitstream compression for Xilinx FPGAs. / Koch, Dirk; Herkersdorf, Andreas (Editor); Wehn, Norbert (Editor); Hubner, Michael (Editor).

Proceedings of the 24th International Conference on Field Programmable Logic and Applications. ed. / Andreas Herkersdorf; Norbert Wehn; Michael Hubner. USA : IEEE, 2014. p. 1-8.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Koch, D, Herkersdorf, A (ed.), Wehn, N (ed.) & Hubner, M (ed.) 2014, Portable module relocation and bitstream compression for Xilinx FPGAs. in A Herkersdorf, N Wehn & M Hubner (eds), Proceedings of the 24th International Conference on Field Programmable Logic and Applications. IEEE, USA, pp. 1-8, Field Programmable Logic and Applications (FPL), Munich, 2/09/14. https://doi.org/10.1109/FPL.2014.6927480

APA

Koch, D., Herkersdorf, A. (Ed.), Wehn, N. (Ed.), & Hubner, M. (Ed.) (2014). Portable module relocation and bitstream compression for Xilinx FPGAs. In A. Herkersdorf, N. Wehn, & M. Hubner (Eds.), Proceedings of the 24th International Conference on Field Programmable Logic and Applications (pp. 1-8). IEEE. https://doi.org/10.1109/FPL.2014.6927480

Vancouver

Koch D, Herkersdorf A, (ed.), Wehn N, (ed.), Hubner M, (ed.). Portable module relocation and bitstream compression for Xilinx FPGAs. In Herkersdorf A, Wehn N, Hubner M, editors, Proceedings of the 24th International Conference on Field Programmable Logic and Applications. USA: IEEE. 2014. p. 1-8 https://doi.org/10.1109/FPL.2014.6927480

Author

Koch, Dirk ; Herkersdorf, Andreas (Editor) ; Wehn, Norbert (Editor) ; Hubner, Michael (Editor). / Portable module relocation and bitstream compression for Xilinx FPGAs. Proceedings of the 24th International Conference on Field Programmable Logic and Applications. editor / Andreas Herkersdorf ; Norbert Wehn ; Michael Hubner. USA : IEEE, 2014. pp. 1-8

Bibtex

@inproceedings{45c0517ccbf846ee8e36a385efb49687,
title = "Portable module relocation and bitstream compression for Xilinx FPGAs",
abstract = "This paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. The presented methodology for bitstream generation and compression does not need deep knowledge of the bitstream format and it is independent of the target (Xilinx) FPGA family. The approach consists of a design phase where partial bitstreams are decomposed into sequences of module dependent and module independent pieces of configuration data. At run-time, this data can then be recomposed for the individual placement positions by a special DMA configuration controller as one atomic operation without any further software interaction. Our experiments demonstrate that module relocation and fast partial reconfiguration can be implemented at low logic cost.",
keywords = "FPGA Configurtion, Bitstream Compression",
author = "Dirk Koch and Andreas Herkersdorf and Norbert Wehn and Michael Hubner",
year = "2014",
month = sep,
doi = "10.1109/FPL.2014.6927480",
language = "English",
pages = "1--8",
editor = "Andreas Herkersdorf and Norbert Wehn and Michael Hubner",
booktitle = "Proceedings of the 24th International Conference on Field Programmable Logic and Applications",
publisher = "IEEE",
address = "United States",
note = "Field Programmable Logic and Applications (FPL) ; Conference date: 02-09-2014 Through 04-09-2014",

}

RIS

TY - GEN

T1 - Portable module relocation and bitstream compression for Xilinx FPGAs

AU - Koch, Dirk

A2 - Herkersdorf, Andreas

A2 - Wehn, Norbert

A2 - Hubner, Michael

A2 - Herkersdorf, Andreas

A2 - Wehn, Norbert

A2 - Hubner, Michael

PY - 2014/9

Y1 - 2014/9

N2 - This paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. The presented methodology for bitstream generation and compression does not need deep knowledge of the bitstream format and it is independent of the target (Xilinx) FPGA family. The approach consists of a design phase where partial bitstreams are decomposed into sequences of module dependent and module independent pieces of configuration data. At run-time, this data can then be recomposed for the individual placement positions by a special DMA configuration controller as one atomic operation without any further software interaction. Our experiments demonstrate that module relocation and fast partial reconfiguration can be implemented at low logic cost.

AB - This paper presents a novel methodology for generating and compressing configuration bitstreams for modules that can be executed at different positions of an FPGA. The presented methodology for bitstream generation and compression does not need deep knowledge of the bitstream format and it is independent of the target (Xilinx) FPGA family. The approach consists of a design phase where partial bitstreams are decomposed into sequences of module dependent and module independent pieces of configuration data. At run-time, this data can then be recomposed for the individual placement positions by a special DMA configuration controller as one atomic operation without any further software interaction. Our experiments demonstrate that module relocation and fast partial reconfiguration can be implemented at low logic cost.

KW - FPGA Configurtion

KW - Bitstream Compression

U2 - 10.1109/FPL.2014.6927480

DO - 10.1109/FPL.2014.6927480

M3 - Conference contribution

SP - 1

EP - 8

BT - Proceedings of the 24th International Conference on Field Programmable Logic and Applications

PB - IEEE

CY - USA

T2 - Field Programmable Logic and Applications (FPL)

Y2 - 2 September 2014 through 4 September 2014

ER -