Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registersCitation formats

  • Authors:
  • J.N.P. Martel
  • M. Chau
  • M. Cook
  • P. Dudek

Standard

Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers. / Martel, J.N.P.; Chau, M.; Cook, M.; Dudek, P.

European Conference on Circuit Theory and Design, ECCTD 2015. IEEE, 2015.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Martel, JNP, Chau, M, Cook, M & Dudek, P 2015, Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers. in European Conference on Circuit Theory and Design, ECCTD 2015. IEEE, European Conference on Circuits Theory and Design, ECCTD 2015, 1/01/24. https://doi.org/10.1109/ECCTD.2015.7300011

APA

Martel, J. N. P., Chau, M., Cook, M., & Dudek, P. (2015). Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers. In European Conference on Circuit Theory and Design, ECCTD 2015 IEEE. https://doi.org/10.1109/ECCTD.2015.7300011

Vancouver

Martel JNP, Chau M, Cook M, Dudek P. Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers. In European Conference on Circuit Theory and Design, ECCTD 2015. IEEE. 2015 https://doi.org/10.1109/ECCTD.2015.7300011

Author

Martel, J.N.P. ; Chau, M. ; Cook, M. ; Dudek, P. / Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers. European Conference on Circuit Theory and Design, ECCTD 2015. IEEE, 2015.

Bibtex

@inproceedings{9dda0429ae6748c6a6070a61740c4f7c,
title = "Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers",
abstract = "Recently, several low and mid-level vision algorithms have been successfully demonstrated at high-frame rate on a low power-budget using compact programmable CPA (Cellular Processor Arrays) vision-chips that embed a Processing Element (PE) at each pixel. Because of the inherent constraint in the VLSI design of these devices, algorithms they run are limited to scarce resources, in particular memory - that is the number of registers available per pixel. In this work, we propose an algorithmic procedure to trade off the pixel resolution of a programmable CPA vision-chip against the number of its registers. By grouping pixels into “super-pixels” where pixel registers are interlaced, we virtually expose more registers in software allowing to run more sophisticated algorithms. We implement and demonstrate on an actual device an algorithm that could not have been executed on an existing CPA at full resolution due to its memory requirements.",
author = "J.N.P. Martel and M. Chau and M. Cook and P. Dudek",
year = "2015",
month = "9",
doi = "10.1109/ECCTD.2015.7300011",
language = "English",
booktitle = "European Conference on Circuit Theory and Design, ECCTD 2015",
publisher = "IEEE",
address = "United States",

}

RIS

TY - GEN

T1 - Pixel interlacing to trade off the resolution of a Cellular Processor Array against more registers

AU - Martel, J.N.P.

AU - Chau, M.

AU - Cook, M.

AU - Dudek, P.

PY - 2015/9

Y1 - 2015/9

N2 - Recently, several low and mid-level vision algorithms have been successfully demonstrated at high-frame rate on a low power-budget using compact programmable CPA (Cellular Processor Arrays) vision-chips that embed a Processing Element (PE) at each pixel. Because of the inherent constraint in the VLSI design of these devices, algorithms they run are limited to scarce resources, in particular memory - that is the number of registers available per pixel. In this work, we propose an algorithmic procedure to trade off the pixel resolution of a programmable CPA vision-chip against the number of its registers. By grouping pixels into “super-pixels” where pixel registers are interlaced, we virtually expose more registers in software allowing to run more sophisticated algorithms. We implement and demonstrate on an actual device an algorithm that could not have been executed on an existing CPA at full resolution due to its memory requirements.

AB - Recently, several low and mid-level vision algorithms have been successfully demonstrated at high-frame rate on a low power-budget using compact programmable CPA (Cellular Processor Arrays) vision-chips that embed a Processing Element (PE) at each pixel. Because of the inherent constraint in the VLSI design of these devices, algorithms they run are limited to scarce resources, in particular memory - that is the number of registers available per pixel. In this work, we propose an algorithmic procedure to trade off the pixel resolution of a programmable CPA vision-chip against the number of its registers. By grouping pixels into “super-pixels” where pixel registers are interlaced, we virtually expose more registers in software allowing to run more sophisticated algorithms. We implement and demonstrate on an actual device an algorithm that could not have been executed on an existing CPA at full resolution due to its memory requirements.

U2 - 10.1109/ECCTD.2015.7300011

DO - 10.1109/ECCTD.2015.7300011

M3 - Conference contribution

BT - European Conference on Circuit Theory and Design, ECCTD 2015

PB - IEEE

ER -