On-chip timing reference for self-timed microprocessor

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A calibratable on-chip timing reference circuit has been developed to enable a self-timed microprocessor to interface to standard offchip memory and peripheral devices. The circuit exhibits several of the desirable properties of self-timed circuitry such as low power consumption and low electromagnetic interference (EMI). In addition, it is highly testable.

Bibliographical metadata

Original languageEnglish
Pages (from-to)942-943
Number of pages2
JournalElectronics Letters
Issue number11
Publication statusPublished - 25 May 2000