Silicon Photonic interconnects are a promising technology for scaling computing
systems into the exa-scale domain. However, there exist significant challenges
in terms of optical losses and complexity. In this work, we evaluate the applicability of a thermally/electrically tuned Beneš network based on Mach-Zehnder Interferometers for on-chip and inter-chip interconnects as regards its scalability.
We examine how insertion loss, laser power and switching energy consumption
scale with the number of endpoints. In addition, we propose a set of hardware inspired routing strategies that leverage the inherent asymmetry present in the
switching components. We evaluate a range of network sizes, from 16 up to 256
endpoints, using 8 realistic and synthetic workloads and found very promising
results. Our routing strategies offer a reduction in path-dependent insertion
loss of up to 35% in the best case, as well as a laser power reduction of 31% for
32 endpoints. In addition, bit-switching energy is reduced by between 8% and
15% using the most efficient routing strategy, depending on the communication
workload. We also show that workload execution time can be reduced with
the best strategies by 5-25% in some workloads, while the worst-case increases
are at most 3%. Using our routing strategies, we show that under the examined technology parameters, a 32-endpoint interconnect can be considered for
the NoC domain in terms of insertion loss and laser power, even when using
conservative parameters for the modulator.