Modeling cache sharing on chip multiprocessor architecturesCitation formats

  • Authors:
  • Pavios Petoumenos
  • Georgios Keramidas
  • Håkan Zeffer
  • Stefanos Kaxiras
  • Erik Hagersten

Standard

Modeling cache sharing on chip multiprocessor architectures. / Petoumenos, Pavios; Keramidas, Georgios; Zeffer, Håkan; Kaxiras, Stefanos; Hagersten, Erik.

Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006. IEEE, 2006. p. 160-171 4086144.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Harvard

Petoumenos, P, Keramidas, G, Zeffer, H, Kaxiras, S & Hagersten, E 2006, Modeling cache sharing on chip multiprocessor architectures. in Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006., 4086144, IEEE, pp. 160-171, IEEE International Symposium on Workload Characterization, San Jose, United States, 25/10/06. https://doi.org/10.1109/IISWC.2006.302740

APA

Petoumenos, P., Keramidas, G., Zeffer, H., Kaxiras, S., & Hagersten, E. (2006). Modeling cache sharing on chip multiprocessor architectures. In Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006 (pp. 160-171). [4086144] IEEE. https://doi.org/10.1109/IISWC.2006.302740

Vancouver

Petoumenos P, Keramidas G, Zeffer H, Kaxiras S, Hagersten E. Modeling cache sharing on chip multiprocessor architectures. In Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006. IEEE. 2006. p. 160-171. 4086144 https://doi.org/10.1109/IISWC.2006.302740

Author

Petoumenos, Pavios ; Keramidas, Georgios ; Zeffer, Håkan ; Kaxiras, Stefanos ; Hagersten, Erik. / Modeling cache sharing on chip multiprocessor architectures. Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006. IEEE, 2006. pp. 160-171

Bibtex

@inproceedings{6b5b89cfbdc54285a658cd56c7466ce1,
title = "Modeling cache sharing on chip multiprocessor architectures",
abstract = "As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip resources, such as shared caches, becomes a necessity. In this paper we propose a new statistical model of a CMP shared cache which not only describes cache sharing but also its management via a novel fine-grain mechanism. Our model, called StatShare, accurately describes the behavior of the sharing threads using run-time information (reuse-distance information for memory accesses) and helps us understand how effectively each thread uses its space. The mechanism to manage the cache at the cache-line granularity is inspired by Cache Decay, but contains important differences. Decayed cache-lines are not turned-off to save leakage but are rather {"}available for replacement.{"} Decay modifies the underlying replacement policy (random, LRU) to control sharing but in a very flexible and non-strict way which makes it superior to strict cache partitioning schemes (both fine and coarse grained). The statistical model allows us to assess a thread's cache behavior under decay. Detailed CMP simulations show that: i) StatShare accurately predicts the thread behavior in a shared cache, ii) managing sharing via decay (in combination with the StatShare run time information) can be used to enforce external QoS requirements or various high-level fairness policies.",
author = "Pavios Petoumenos and Georgios Keramidas and H{\aa}kan Zeffer and Stefanos Kaxiras and Erik Hagersten",
year = "2006",
month = dec,
day = "1",
doi = "10.1109/IISWC.2006.302740",
language = "English",
isbn = "1424405084",
pages = "160--171",
booktitle = "Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006",
publisher = "IEEE",
address = "United States",
note = "IEEE International Symposium on Workload Characterization, IISWC-2006 ; Conference date: 25-10-2006 Through 27-10-2006",

}

RIS

TY - GEN

T1 - Modeling cache sharing on chip multiprocessor architectures

AU - Petoumenos, Pavios

AU - Keramidas, Georgios

AU - Zeffer, Håkan

AU - Kaxiras, Stefanos

AU - Hagersten, Erik

PY - 2006/12/1

Y1 - 2006/12/1

N2 - As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip resources, such as shared caches, becomes a necessity. In this paper we propose a new statistical model of a CMP shared cache which not only describes cache sharing but also its management via a novel fine-grain mechanism. Our model, called StatShare, accurately describes the behavior of the sharing threads using run-time information (reuse-distance information for memory accesses) and helps us understand how effectively each thread uses its space. The mechanism to manage the cache at the cache-line granularity is inspired by Cache Decay, but contains important differences. Decayed cache-lines are not turned-off to save leakage but are rather "available for replacement." Decay modifies the underlying replacement policy (random, LRU) to control sharing but in a very flexible and non-strict way which makes it superior to strict cache partitioning schemes (both fine and coarse grained). The statistical model allows us to assess a thread's cache behavior under decay. Detailed CMP simulations show that: i) StatShare accurately predicts the thread behavior in a shared cache, ii) managing sharing via decay (in combination with the StatShare run time information) can be used to enforce external QoS requirements or various high-level fairness policies.

AB - As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip resources, such as shared caches, becomes a necessity. In this paper we propose a new statistical model of a CMP shared cache which not only describes cache sharing but also its management via a novel fine-grain mechanism. Our model, called StatShare, accurately describes the behavior of the sharing threads using run-time information (reuse-distance information for memory accesses) and helps us understand how effectively each thread uses its space. The mechanism to manage the cache at the cache-line granularity is inspired by Cache Decay, but contains important differences. Decayed cache-lines are not turned-off to save leakage but are rather "available for replacement." Decay modifies the underlying replacement policy (random, LRU) to control sharing but in a very flexible and non-strict way which makes it superior to strict cache partitioning schemes (both fine and coarse grained). The statistical model allows us to assess a thread's cache behavior under decay. Detailed CMP simulations show that: i) StatShare accurately predicts the thread behavior in a shared cache, ii) managing sharing via decay (in combination with the StatShare run time information) can be used to enforce external QoS requirements or various high-level fairness policies.

UR - http://www.scopus.com/inward/record.url?scp=48449102571&partnerID=8YFLogxK

U2 - 10.1109/IISWC.2006.302740

DO - 10.1109/IISWC.2006.302740

M3 - Conference contribution

AN - SCOPUS:48449102571

SN - 1424405084

SN - 9781424405084

SP - 160

EP - 171

BT - Proceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006

PB - IEEE

T2 - IEEE International Symposium on Workload Characterization

Y2 - 25 October 2006 through 27 October 2006

ER -