Modeling cache sharing on chip multiprocessor architectures

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  • Authors:
  • Pavios Petoumenos
  • Georgios Keramidas
  • Håkan Zeffer
  • Stefanos Kaxiras
  • Erik Hagersten


As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip resources, such as shared caches, becomes a necessity. In this paper we propose a new statistical model of a CMP shared cache which not only describes cache sharing but also its management via a novel fine-grain mechanism. Our model, called StatShare, accurately describes the behavior of the sharing threads using run-time information (reuse-distance information for memory accesses) and helps us understand how effectively each thread uses its space. The mechanism to manage the cache at the cache-line granularity is inspired by Cache Decay, but contains important differences. Decayed cache-lines are not turned-off to save leakage but are rather "available for replacement." Decay modifies the underlying replacement policy (random, LRU) to control sharing but in a very flexible and non-strict way which makes it superior to strict cache partitioning schemes (both fine and coarse grained). The statistical model allows us to assess a thread's cache behavior under decay. Detailed CMP simulations show that: i) StatShare accurately predicts the thread behavior in a shared cache, ii) managing sharing via decay (in combination with the StatShare run time information) can be used to enforce external QoS requirements or various high-level fairness policies.

Bibliographical metadata

Original languageEnglish
Title of host publicationProceedings of the 2006 IEEE International Symposium on Workload Characterization, IISWC - 2006
Number of pages12
ISBN (Print)1424405084, 9781424405084
Publication statusPublished - 1 Dec 2006
EventIEEE International Symposium on Workload Characterization - San Jose, United States
Event duration: 25 Oct 200627 Oct 2006


ConferenceIEEE International Symposium on Workload Characterization
Abbreviated titleIISWC-2006
CountryUnited States
CitySan Jose