MLP-aware instruction queue resizingCitation formats

  • Authors:
  • Pavlos Petoumenos
  • Georgia Psychou
  • Stefanos Kaxiras
  • Juan Manuel Cebrian Gonzalez
  • Juan Luis Aragon

Standard

MLP-aware instruction queue resizing : the key to power-efficient performance. / Petoumenos, Pavlos; Psychou, Georgia; Kaxiras, Stefanos; Cebrian Gonzalez, Juan Manuel; Aragon, Juan Luis.

Architecture of computing systems - ARCS 2010: 23rd international conference Hannover, Germany, February 22-25, 2010 proceedings. ed. / Christian Müller-Schloer; Wolfgang Karl; Sami Yehia. Berlin, Heidelberg, New York : Springer Nature, 2010. p. 113-125 (Lecture Notes in Computer Science; Vol. 5974).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Harvard

Petoumenos, P, Psychou, G, Kaxiras, S, Cebrian Gonzalez, JM & Aragon, JL 2010, MLP-aware instruction queue resizing: the key to power-efficient performance. in C Müller-Schloer, W Karl & S Yehia (eds), Architecture of computing systems - ARCS 2010: 23rd international conference Hannover, Germany, February 22-25, 2010 proceedings. Lecture Notes in Computer Science, vol. 5974, Springer Nature, Berlin, Heidelberg, New York, pp. 113-125, 23rd International Conference on Architecture of Computing Systems, Hannover, Germany, 22/02/10. https://doi.org/10.1007/978-3-642-11950-7_11

APA

Petoumenos, P., Psychou, G., Kaxiras, S., Cebrian Gonzalez, J. M., & Aragon, J. L. (2010). MLP-aware instruction queue resizing: the key to power-efficient performance. In C. Müller-Schloer, W. Karl, & S. Yehia (Eds.), Architecture of computing systems - ARCS 2010: 23rd international conference Hannover, Germany, February 22-25, 2010 proceedings (pp. 113-125). (Lecture Notes in Computer Science; Vol. 5974). Springer Nature. https://doi.org/10.1007/978-3-642-11950-7_11

Vancouver

Petoumenos P, Psychou G, Kaxiras S, Cebrian Gonzalez JM, Aragon JL. MLP-aware instruction queue resizing: the key to power-efficient performance. In Müller-Schloer C, Karl W, Yehia S, editors, Architecture of computing systems - ARCS 2010: 23rd international conference Hannover, Germany, February 22-25, 2010 proceedings. Berlin, Heidelberg, New York: Springer Nature. 2010. p. 113-125. (Lecture Notes in Computer Science). https://doi.org/10.1007/978-3-642-11950-7_11

Author

Petoumenos, Pavlos ; Psychou, Georgia ; Kaxiras, Stefanos ; Cebrian Gonzalez, Juan Manuel ; Aragon, Juan Luis. / MLP-aware instruction queue resizing : the key to power-efficient performance. Architecture of computing systems - ARCS 2010: 23rd international conference Hannover, Germany, February 22-25, 2010 proceedings. editor / Christian Müller-Schloer ; Wolfgang Karl ; Sami Yehia. Berlin, Heidelberg, New York : Springer Nature, 2010. pp. 113-125 (Lecture Notes in Computer Science).

Bibtex

@inproceedings{b38c6e2b32104c7f9b0e2521552083a6,
title = "MLP-aware instruction queue resizing: the key to power-efficient performance",
abstract = "Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime examples are the techniques to resize the instruction queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the memory-level parallelism (MLP) of the application and thus incur disproportional performance degradation. We propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resizing that does not affect the MLP of the program. This information is used to override the resizing enforced by feedback mechanisms when this resizing might reduce MLP. We compare our technique to a previously proposed non-MLP-aware management technique and our results show a significant increase in EDP savings for most benchmarks of the SPEC2000 suite.",
keywords = "Execution Time, Basic Block, Computer Architecture, Cache Size, Instruction Stream",
author = "Pavlos Petoumenos and Georgia Psychou and Stefanos Kaxiras and {Cebrian Gonzalez}, {Juan Manuel} and Aragon, {Juan Luis}",
year = "2010",
month = dec,
day = "1",
doi = "10.1007/978-3-642-11950-7_11",
language = "English",
isbn = "9783642119491",
series = "Lecture Notes in Computer Science",
publisher = "Springer Nature",
pages = "113--125",
editor = "Christian M{\"u}ller-Schloer and Wolfgang Karl and Sami Yehia",
booktitle = "Architecture of computing systems - ARCS 2010",
address = "United States",
note = "23rd International Conference on Architecture of Computing Systems, ARCS 2010 ; Conference date: 22-02-2010 Through 25-02-2010",

}

RIS

TY - GEN

T1 - MLP-aware instruction queue resizing

T2 - 23rd International Conference on Architecture of Computing Systems

AU - Petoumenos, Pavlos

AU - Psychou, Georgia

AU - Kaxiras, Stefanos

AU - Cebrian Gonzalez, Juan Manuel

AU - Aragon, Juan Luis

PY - 2010/12/1

Y1 - 2010/12/1

N2 - Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime examples are the techniques to resize the instruction queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the memory-level parallelism (MLP) of the application and thus incur disproportional performance degradation. We propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resizing that does not affect the MLP of the program. This information is used to override the resizing enforced by feedback mechanisms when this resizing might reduce MLP. We compare our technique to a previously proposed non-MLP-aware management technique and our results show a significant increase in EDP savings for most benchmarks of the SPEC2000 suite.

AB - Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime examples are the techniques to resize the instruction queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the memory-level parallelism (MLP) of the application and thus incur disproportional performance degradation. We propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resizing that does not affect the MLP of the program. This information is used to override the resizing enforced by feedback mechanisms when this resizing might reduce MLP. We compare our technique to a previously proposed non-MLP-aware management technique and our results show a significant increase in EDP savings for most benchmarks of the SPEC2000 suite.

KW - Execution Time

KW - Basic Block

KW - Computer Architecture

KW - Cache Size

KW - Instruction Stream

UR - http://www.scopus.com/inward/record.url?scp=78651259285&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-11950-7_11

DO - 10.1007/978-3-642-11950-7_11

M3 - Conference contribution

AN - SCOPUS:78651259285

SN - 9783642119491

T3 - Lecture Notes in Computer Science

SP - 113

EP - 125

BT - Architecture of computing systems - ARCS 2010

A2 - Müller-Schloer, Christian

A2 - Karl, Wolfgang

A2 - Yehia, Sami

PB - Springer Nature

CY - Berlin, Heidelberg, New York

Y2 - 22 February 2010 through 25 February 2010

ER -