Mismatch Compensation Technique for Inverter-Based CMOS CircuitsCitation formats

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Mismatch Compensation Technique for Inverter-Based CMOS Circuits. / Mroszczyk, Przemyslaw; Pavlidis, Vasileios.

IEEE International Symposium on Circuits and Systems. 2018.

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Mroszczyk, Przemyslaw ; Pavlidis, Vasileios. / Mismatch Compensation Technique for Inverter-Based CMOS Circuits. IEEE International Symposium on Circuits and Systems. 2018.

Bibtex

@inproceedings{deec66fbe4cb4c999280d82b8449cddf,
title = "Mismatch Compensation Technique for Inverter-Based CMOS Circuits",
abstract = "Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using model: from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy and area, and compared against the geometry scaling approach.",
author = "Przemyslaw Mroszczyk and Vasileios Pavlidis",
year = "2018",
doi = "10.1109/ISCAS.2018.8351057",
language = "English",
booktitle = "IEEE International Symposium on Circuits and Systems",

}

RIS

TY - GEN

T1 - Mismatch Compensation Technique for Inverter-Based CMOS Circuits

AU - Mroszczyk, Przemyslaw

AU - Pavlidis, Vasileios

PY - 2018

Y1 - 2018

N2 - Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using model: from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy and area, and compared against the geometry scaling approach.

AB - Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using model: from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy and area, and compared against the geometry scaling approach.

U2 - 10.1109/ISCAS.2018.8351057

DO - 10.1109/ISCAS.2018.8351057

M3 - Conference contribution

BT - IEEE International Symposium on Circuits and Systems

ER -