Mismatch Compensation Technique for Inverter-Based CMOS Circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Inverter-based CMOS circuits are often considered in the front-end modules for optical and wireline communication A-D conversion, and analogue computation. Due to parameter variability (mismatch), the performance of such circuits is usually degraded. This paper presents a mismatch compensation technique employing a set of redundant switches to trim the switching threshold of inverter-based CMOS circuits. Over 10× better parameter matching is observed at no additional energy cost or significant gate area increase, compared to “traditional” geometry scaling. The efficiency of the mismatch compensation is investigated across a broad design space considering the number and size of the switches, and the size of the inverter, using model: from a 65 nm CMOS technology. The case study of a comparator circuit is further investigated in terms of the reliability, energy and area, and compared against the geometry scaling approach.

Bibliographical metadata

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 2018