Managing a massively-parallel resource-constrained computing architectureCitation formats

  • Authors:
  • Cameron Patterson
  • Thomas Preston
  • Francesco Galluppi
  • Steve Furber

Standard

Managing a massively-parallel resource-constrained computing architecture. / Patterson, Cameron; Preston, Thomas; Galluppi, Francesco; Furber, Steve.

Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD. 2012. p. 723-726.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Patterson, C, Preston, T, Galluppi, F & Furber, S 2012, Managing a massively-parallel resource-constrained computing architecture. in Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD. pp. 723-726, 15th Euromicro Conference on Digital System Design, DSD 2012, Cesme, Izmir, 1/07/12. https://doi.org/10.1109/DSD.2012.84

APA

Patterson, C., Preston, T., Galluppi, F., & Furber, S. (2012). Managing a massively-parallel resource-constrained computing architecture. In Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD (pp. 723-726) https://doi.org/10.1109/DSD.2012.84

Vancouver

Patterson C, Preston T, Galluppi F, Furber S. Managing a massively-parallel resource-constrained computing architecture. In Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD. 2012. p. 723-726 https://doi.org/10.1109/DSD.2012.84

Author

Patterson, Cameron ; Preston, Thomas ; Galluppi, Francesco ; Furber, Steve. / Managing a massively-parallel resource-constrained computing architecture. Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD. 2012. pp. 723-726

Bibtex

@inproceedings{8d2d633a807d44ebb15f3f88aa5e2519,
title = "Managing a massively-parallel resource-constrained computing architecture",
abstract = "One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. {\textcopyright} 2012 IEEE.",
keywords = "Computer performance, Embedded, High performance computing, Middleboxes, Monitoring",
author = "Cameron Patterson and Thomas Preston and Francesco Galluppi and Steve Furber",
year = "2012",
doi = "10.1109/DSD.2012.84",
language = "English",
isbn = "9780769547985",
pages = "723--726",
booktitle = "Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD",
note = "15th Euromicro Conference on Digital System Design, DSD 2012 ; Conference date: 01-07-2012",

}

RIS

TY - GEN

T1 - Managing a massively-parallel resource-constrained computing architecture

AU - Patterson, Cameron

AU - Preston, Thomas

AU - Galluppi, Francesco

AU - Furber, Steve

PY - 2012

Y1 - 2012

N2 - One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. © 2012 IEEE.

AB - One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker. © 2012 IEEE.

KW - Computer performance

KW - Embedded

KW - High performance computing

KW - Middleboxes

KW - Monitoring

U2 - 10.1109/DSD.2012.84

DO - 10.1109/DSD.2012.84

M3 - Conference contribution

SN - 9780769547985

SP - 723

EP - 726

BT - Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012|Proc. - Euromicro Conf. Digit. Syst. Des., DSD

T2 - 15th Euromicro Conference on Digital System Design, DSD 2012

Y2 - 1 July 2012

ER -