MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management

Research output: Contribution to journalArticlepeer-review

  • External authors:
  • Jalil Boukhobza
  • Stéphane Rubini
  • Laurent Lemarchand
  • Yassine Hadjadj-aoul
  • Arezki Laga

Abstract

Flash memories based storage systems have some specific constraints leading designers to encapsulate some management services into a hardware/software layer called the Flash Translation Layer (FTL). The performance of flash based storage systems such as Solid State Drives (SSDs) are strongly driven by the FTL intricacies and also by a cache system placed on top of the FTL. Those systems are generally developed independently. In order to accelerate I/O request processing, FTLs use some space of the flash memory called the over-provisioning space. The over-provisioning space is thus not dedicated to data storage and should be small and of fixed size. This paper presents MaCACH, a maximum page-mapped region usage, cache-aware, and configurable hybrid mapping scheme. MaCACH design is based on two motivations: (1) the FTL should make full profit of the fixed size over-provisioning space to accelerate I/O processing, (2) as in most cases cache systems are put on top of FTLs, the latter should use information about the former in order to optimize data management. MaCACH is mainly based on two solutions: (1) it uses a proportional–integral–derivative (PID) feedback control system to keep the over-provisioning space fully used whatever the I/O workload characteristics, making it more efficient, (2) it is cache-aware as it uses a common feature of flash specific caches in order to route evicted data toward a page-mapped or block-mapped area which helps in optimizing the write operation costs. The performance evaluation shows very good behavior of MaCACH as compared to state-of-the-art FTLs in addition to a high flexibility as MaCACH has a large

Bibliographical metadata

Original languageEnglish
Pages (from-to)157-171
JournalJournal of Systems Architecture
Volume61
Issue number3-4
DOIs
Publication statusPublished - 27 Mar 2015