Low Overhead Dynamic Binary Translation on ARMCitation formats

  • Authors:
  • Amanieu d'Antras
  • Cosmin Gorgovan
  • Jim Garside
  • Mikel Luján

Standard

Low Overhead Dynamic Binary Translation on ARM. / d'Antras, Amanieu; Gorgovan, Cosmin; Garside, Jim; Luján, Mikel.

Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017. Association for Computing Machinery, 2017. p. 333–346.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

d'Antras, A, Gorgovan, C, Garside, J & Luján, M 2017, Low Overhead Dynamic Binary Translation on ARM. in Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017. Association for Computing Machinery, pp. 333–346. https://doi.org/10.1145/3062341.3062371

APA

d'Antras, A., Gorgovan, C., Garside, J., & Luján, M. (2017). Low Overhead Dynamic Binary Translation on ARM. In Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017 (pp. 333–346). Association for Computing Machinery. https://doi.org/10.1145/3062341.3062371

Vancouver

d'Antras A, Gorgovan C, Garside J, Luján M. Low Overhead Dynamic Binary Translation on ARM. In Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017. Association for Computing Machinery. 2017. p. 333–346 https://doi.org/10.1145/3062341.3062371

Author

d'Antras, Amanieu ; Gorgovan, Cosmin ; Garside, Jim ; Luján, Mikel. / Low Overhead Dynamic Binary Translation on ARM. Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017. Association for Computing Machinery, 2017. pp. 333–346

Bibtex

@inproceedings{8dc24898a89745ac84d99505293cdf65,
title = "Low Overhead Dynamic Binary Translation on ARM",
abstract = "The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction set, while retaining binary compatibility with previous versions of the ARM architecture through AArch32, a 32-bit execution mode. Most hardware implementations of ARMv8 processors support both AArch32 and AArch64, which comes at a cost in hardware complexity.We present MAMBO-X64, a dynamic binary translator for Linux which executes 32-bit ARM binaries using only the AArch64 instruction set. We have evaluated the performance of MAMBO-X64 on three existing ARMv8 processors which support both AArch32 and AArch64 instruction sets. The performance was measured by comparing the running time of 32-bit benchmarks running under MAMBO-X64 with the same benchmark running natively. On SPEC CPU2006, we achieve a geometric mean overhead of less than 7.5 % on in-order Cortex-A53 processors and a performance improvement of 1 % on out-of-order X-Gene 1 processors.MAMBO-X64 achieves such low overhead by novel optimizations to map AArch32 floating-point registers to AArch64 registers dynamically, handle overflowing address calculations efficiently, generate traces that harness hardware return address prediction, and handle operating system signals accurately.",
author = "Amanieu d'Antras and Cosmin Gorgovan and Jim Garside and Mikel Luj{\'a}n",
year = "2017",
month = jun,
day = "18",
doi = "10.1145/3062341.3062371",
language = "English",
isbn = "978-1-4503-4988-8",
pages = "333–346",
booktitle = "Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017",
publisher = "Association for Computing Machinery",
address = "United States",

}

RIS

TY - GEN

T1 - Low Overhead Dynamic Binary Translation on ARM

AU - d'Antras, Amanieu

AU - Gorgovan, Cosmin

AU - Garside, Jim

AU - Luján, Mikel

PY - 2017/6/18

Y1 - 2017/6/18

N2 - The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction set, while retaining binary compatibility with previous versions of the ARM architecture through AArch32, a 32-bit execution mode. Most hardware implementations of ARMv8 processors support both AArch32 and AArch64, which comes at a cost in hardware complexity.We present MAMBO-X64, a dynamic binary translator for Linux which executes 32-bit ARM binaries using only the AArch64 instruction set. We have evaluated the performance of MAMBO-X64 on three existing ARMv8 processors which support both AArch32 and AArch64 instruction sets. The performance was measured by comparing the running time of 32-bit benchmarks running under MAMBO-X64 with the same benchmark running natively. On SPEC CPU2006, we achieve a geometric mean overhead of less than 7.5 % on in-order Cortex-A53 processors and a performance improvement of 1 % on out-of-order X-Gene 1 processors.MAMBO-X64 achieves such low overhead by novel optimizations to map AArch32 floating-point registers to AArch64 registers dynamically, handle overflowing address calculations efficiently, generate traces that harness hardware return address prediction, and handle operating system signals accurately.

AB - The ARMv8 architecture introduced AArch64, a 64-bit execution mode with a new instruction set, while retaining binary compatibility with previous versions of the ARM architecture through AArch32, a 32-bit execution mode. Most hardware implementations of ARMv8 processors support both AArch32 and AArch64, which comes at a cost in hardware complexity.We present MAMBO-X64, a dynamic binary translator for Linux which executes 32-bit ARM binaries using only the AArch64 instruction set. We have evaluated the performance of MAMBO-X64 on three existing ARMv8 processors which support both AArch32 and AArch64 instruction sets. The performance was measured by comparing the running time of 32-bit benchmarks running under MAMBO-X64 with the same benchmark running natively. On SPEC CPU2006, we achieve a geometric mean overhead of less than 7.5 % on in-order Cortex-A53 processors and a performance improvement of 1 % on out-of-order X-Gene 1 processors.MAMBO-X64 achieves such low overhead by novel optimizations to map AArch32 floating-point registers to AArch64 registers dynamically, handle overflowing address calculations efficiently, generate traces that harness hardware return address prediction, and handle operating system signals accurately.

U2 - 10.1145/3062341.3062371

DO - 10.1145/3062341.3062371

M3 - Conference contribution

SN - 978-1-4503-4988-8

SP - 333

EP - 346

BT - Proceedings of the 38th ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2017

PB - Association for Computing Machinery

ER -