Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systemsCitation formats

  • External authors:
  • Sebastian Höppner
  • Yexin Yan
  • Bernhard Vogginger
  • Andreas Dixius
  • Johannes Partzsch
  • Prateek Joshi
  • Felix Neumärker
  • Stephan Hartmann
  • Stefan Schiefer
  • Stefan Scholze
  • Georg Ellguth
  • Love Cederstroem
  • Matthias Eberlein
  • Christian Mayr
  • Steven Temple

Standard

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. / Höppner, Sebastian; Yan, Yexin; Vogginger, Bernhard; Dixius, Andreas; Partzsch, Johannes; Joshi, Prateek; Neumärker, Felix; Hartmann, Stephan; Schiefer, Stefan; Scholze, Stefan; Ellguth, Georg; Cederstroem, Love; Eberlein, Matthias; Mayr, Christian; Temple, Steven; Plana, Luis A.; Garside, James; Davidson, Simon; Lester, David; Furber, Stephen.

2017. Poster session presented at IEEE International Symposium on Circuits and Systems, Baltimore, United States.

Research output: Contribution to conference › Poster › peer-review

Harvard

Höppner, S, Yan, Y, Vogginger, B, Dixius, A, Partzsch, J, Joshi, P, Neumärker, F, Hartmann, S, Schiefer, S, Scholze, S, Ellguth, G, Cederstroem, L, Eberlein, M, Mayr, C, Temple, S, Plana, LA, Garside, J, Davidson, S, Lester, D & Furber, S 2017, 'Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems', IEEE International Symposium on Circuits and Systems, Baltimore, United States, 28/05/17 - 31/05/17. https://doi.org/10.1109/ISCAS.2017.8050396

APA

Höppner, S., Yan, Y., Vogginger, B., Dixius, A., Partzsch, J., Joshi, P., Neumärker, F., Hartmann, S., Schiefer, S., Scholze, S., Ellguth, G., Cederstroem, L., Eberlein, M., Mayr, C., Temple, S., Plana, L. A., Garside, J., Davidson, S., Lester, D., & Furber, S. (2017). Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. Poster session presented at IEEE International Symposium on Circuits and Systems, Baltimore, United States. https://doi.org/10.1109/ISCAS.2017.8050396

Vancouver

Höppner S, Yan Y, Vogginger B, Dixius A, Partzsch J, Joshi P et al. Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. 2017. Poster session presented at IEEE International Symposium on Circuits and Systems, Baltimore, United States. https://doi.org/10.1109/ISCAS.2017.8050396

Author

Höppner, Sebastian ; Yan, Yexin ; Vogginger, Bernhard ; Dixius, Andreas ; Partzsch, Johannes ; Joshi, Prateek ; Neumärker, Felix ; Hartmann, Stephan ; Schiefer, Stefan ; Scholze, Stefan ; Ellguth, Georg ; Cederstroem, Love ; Eberlein, Matthias ; Mayr, Christian ; Temple, Steven ; Plana, Luis A. ; Garside, James ; Davidson, Simon ; Lester, David ; Furber, Stephen. / Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. Poster session presented at IEEE International Symposium on Circuits and Systems, Baltimore, United States.

Bibtex

@conference{25ade906b6594de5b05aca18bba896a4,
title = "Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems",
abstract = "We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark — the synfire chain — we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.",
keywords = "MPSoC, neuromorphic computing, power management, DVFS, synfire chain",
author = "Sebastian H{\"o}ppner and Yexin Yan and Bernhard Vogginger and Andreas Dixius and Johannes Partzsch and Prateek Joshi and Felix Neum{\"a}rker and Stephan Hartmann and Stefan Schiefer and Stefan Scholze and Georg Ellguth and Love Cederstroem and Matthias Eberlein and Christian Mayr and Steven Temple and Plana, {Luis A.} and James Garside and Simon Davidson and David Lester and Stephen Furber",
year = "2017",
doi = "10.1109/ISCAS.2017.8050396",
language = "English",
note = "IEEE International Symposium on Circuits and Systems : From Dreams to Innovation, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",
url = "http://iscas2017.org/",

}

RIS

TY - CONF

T1 - Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

AU - Höppner, Sebastian

AU - Yan, Yexin

AU - Vogginger, Bernhard

AU - Dixius, Andreas

AU - Partzsch, Johannes

AU - Joshi, Prateek

AU - Neumärker, Felix

AU - Hartmann, Stephan

AU - Schiefer, Stefan

AU - Scholze, Stefan

AU - Ellguth, Georg

AU - Cederstroem, Love

AU - Eberlein, Matthias

AU - Mayr, Christian

AU - Temple, Steven

AU - Plana, Luis A.

AU - Garside, James

AU - Davidson, Simon

AU - Lester, David

AU - Furber, Stephen

PY - 2017

Y1 - 2017

N2 - We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark — the synfire chain — we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.

AB - We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark — the synfire chain — we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.

KW - MPSoC

KW - neuromorphic computing

KW - power management

KW - DVFS

KW - synfire chain

U2 - 10.1109/ISCAS.2017.8050396

DO - 10.1109/ISCAS.2017.8050396

M3 - Poster

T2 - IEEE International Symposium on Circuits and Systems

Y2 - 28 May 2017 through 31 May 2017

ER -