Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

Research output: Contribution to conferencePosterpeer-review

  • External authors:
  • Sebastian Höppner
  • Yexin Yan
  • Bernhard Vogginger
  • Andreas Dixius
  • Johannes Partzsch
  • Prateek Joshi
  • Felix Neumärker
  • Stephan Hartmann
  • Stefan Schiefer
  • Stefan Scholze
  • Georg Ellguth
  • Love Cederstroem
  • Matthias Eberlein
  • Christian Mayr
  • Steven Temple


We present a dynamic voltage and frequency scaling technique within SoCs for per-core power management: the architecture allows for individual, self triggered performance-level scaling of the processing elements (PEs) within less than 100ns. This technique enables each core to adjust its local supply voltage and frequency depending on its current computational load. A test chip has been implemented in 28nm CMOS technology, as prototype of the SpiNNaker2 neuromorphic many core system, containing 4 PEs which are operational within the range of 1.1V down to 0.7V at frequencies from 666MHz down to 100MHz; The particular domain area of this application specific processor is real-time neuromorphics. Using a standard benchmark — the synfire chain — we show that the total power consumption can be reduced by 45%, with 85% baseline power reduction and a 30% reduction of energy per neuron and synapse computation, all while maintaining biological real-time operation.

Bibliographical metadata

Original languageEnglish
Publication statusPublished - 2017
EventIEEE International Symposium on Circuits and Systems: From Dreams to Innovation - Baltimore, United States
Event duration: 28 May 201731 May 2017


ConferenceIEEE International Symposium on Circuits and Systems
Abbreviated titleISCAS 2017
CountryUnited States
Internet address