Implementing learning on the SpiNNaker universal neural chip multiprocessorCitation formats

  • Authors:
  • Xin Jin
  • Alexander Rast
  • Francesco Galluppi
  • M. Mukaram Khan
  • Stephen Furber

Standard

Implementing learning on the SpiNNaker universal neural chip multiprocessor. / Jin, Xin; Rast, Alexander; Galluppi, Francesco; Khan, M. Mukaram; Furber, Stephen.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 5863 LNCS PART 1. ed. 2009. p. 425-432 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5863 LNCS, No. PART 1).

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Jin, X, Rast, A, Galluppi, F, Khan, MM & Furber, S 2009, Implementing learning on the SpiNNaker universal neural chip multiprocessor. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 1 edn, vol. 5863 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), no. PART 1, vol. 5863 LNCS, pp. 425-432, 16th International Conference on Neural Information Processing, ICONIP 2009, Bangkok, Thailand, 1/12/09. https://doi.org/10.1007/978-3-642-10677-4_48

APA

Jin, X., Rast, A., Galluppi, F., Khan, M. M., & Furber, S. (2009). Implementing learning on the SpiNNaker universal neural chip multiprocessor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (PART 1 ed., Vol. 5863 LNCS, pp. 425-432). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5863 LNCS, No. PART 1). https://doi.org/10.1007/978-3-642-10677-4_48

Vancouver

Jin X, Rast A, Galluppi F, Khan MM, Furber S. Implementing learning on the SpiNNaker universal neural chip multiprocessor. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 1 ed. Vol. 5863 LNCS. 2009. p. 425-432. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); PART 1). https://doi.org/10.1007/978-3-642-10677-4_48

Author

Jin, Xin ; Rast, Alexander ; Galluppi, Francesco ; Khan, M. Mukaram ; Furber, Stephen. / Implementing learning on the SpiNNaker universal neural chip multiprocessor. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 5863 LNCS PART 1. ed. 2009. pp. 425-432 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); PART 1).

Bibtex

@inproceedings{d9532ae31d044f56bb188edb452d2617,
title = "Implementing learning on the SpiNNaker universal neural chip multiprocessor",
abstract = "Large-scale neural simulation requires high-performance hardware with on-chip learning. Using SpiNNaker, a universal neural network chip multiprocessor, we demonstrate an STDP implementation as an example of programmable on-chip learning for dedicated neural hardware. Using a scheme driven entirely by pre-synaptic spike events, we optimize both the data representation and processing for efficiency of implementation. The deferred-event model provides a reconfigurable timing record length to meet different accuracy requirements. Results demonstrate successful STDP within a multi-chip simulation containing 60 neurons and 240 synapses. This optimisable learning model illustrates the scalable general-purpose techniques essential for developing functional learning rules on general-purpose, parallel neural hardware.",
keywords = "Event-Driven, Learning, Neural, Spiking, SpiNNaker, STDP",
author = "Xin Jin and Alexander Rast and Francesco Galluppi and Khan, {M. Mukaram} and Stephen Furber",
year = "2009",
doi = "10.1007/978-3-642-10677-4_48",
language = "English",
isbn = "3642106765",
volume = "5863 LNCS",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
number = "PART 1",
pages = "425--432",
booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
edition = "PART 1",
note = "16th International Conference on Neural Information Processing, ICONIP 2009 ; Conference date: 01-12-2009 Through 05-12-2009",

}

RIS

TY - GEN

T1 - Implementing learning on the SpiNNaker universal neural chip multiprocessor

AU - Jin, Xin

AU - Rast, Alexander

AU - Galluppi, Francesco

AU - Khan, M. Mukaram

AU - Furber, Stephen

PY - 2009

Y1 - 2009

N2 - Large-scale neural simulation requires high-performance hardware with on-chip learning. Using SpiNNaker, a universal neural network chip multiprocessor, we demonstrate an STDP implementation as an example of programmable on-chip learning for dedicated neural hardware. Using a scheme driven entirely by pre-synaptic spike events, we optimize both the data representation and processing for efficiency of implementation. The deferred-event model provides a reconfigurable timing record length to meet different accuracy requirements. Results demonstrate successful STDP within a multi-chip simulation containing 60 neurons and 240 synapses. This optimisable learning model illustrates the scalable general-purpose techniques essential for developing functional learning rules on general-purpose, parallel neural hardware.

AB - Large-scale neural simulation requires high-performance hardware with on-chip learning. Using SpiNNaker, a universal neural network chip multiprocessor, we demonstrate an STDP implementation as an example of programmable on-chip learning for dedicated neural hardware. Using a scheme driven entirely by pre-synaptic spike events, we optimize both the data representation and processing for efficiency of implementation. The deferred-event model provides a reconfigurable timing record length to meet different accuracy requirements. Results demonstrate successful STDP within a multi-chip simulation containing 60 neurons and 240 synapses. This optimisable learning model illustrates the scalable general-purpose techniques essential for developing functional learning rules on general-purpose, parallel neural hardware.

KW - Event-Driven

KW - Learning

KW - Neural

KW - Spiking

KW - SpiNNaker

KW - STDP

UR - http://www.scopus.com/inward/record.url?scp=76649135818&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-10677-4_48

DO - 10.1007/978-3-642-10677-4_48

M3 - Conference contribution

AN - SCOPUS:76649135818

SN - 3642106765

SN - 9783642106767

VL - 5863 LNCS

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 425

EP - 432

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

T2 - 16th International Conference on Neural Information Processing, ICONIP 2009

Y2 - 1 December 2009 through 5 December 2009

ER -