Large-scale neural simulation requires high-performance hardware with on-chip learning. Using SpiNNaker, a universal neural network chip multiprocessor, we demonstrate an STDP implementation as an example of programmable on-chip learning for dedicated neural hardware. Using a scheme driven entirely by pre-synaptic spike events, we optimize both the data representation and processing for efficiency of implementation. The deferred-event model provides a reconfigurable timing record length to meet different accuracy requirements. Results demonstrate successful STDP within a multi-chip simulation containing 60 neurons and 240 synapses. This optimisable learning model illustrates the scalable general-purpose techniques essential for developing functional learning rules on general-purpose, parallel neural hardware.