Hierarchical reconfiguration of FPGAsCitation formats

  • Authors:
  • Dirk Koch
  • Andreas Herkersdorf (Editor)

Standard

Hierarchical reconfiguration of FPGAs. / Koch, Dirk; Herkersdorf, Andreas (Editor).

Proceedings of the 24th International Conference on Field Programmable Logic and Applications. ed. / Andreas Herkersdorf. USA : IEEE, 2014. p. 1-8.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Koch, D & Herkersdorf, A (ed.) 2014, Hierarchical reconfiguration of FPGAs. in A Herkersdorf (ed.), Proceedings of the 24th International Conference on Field Programmable Logic and Applications. IEEE, USA, pp. 1-8, Field Programmable Logic and Applications (FPL), Munich, 2/09/14. https://doi.org/10.1109/FPL.2014.6927491

APA

Koch, D., & Herkersdorf, A. (Ed.) (2014). Hierarchical reconfiguration of FPGAs. In A. Herkersdorf (Ed.), Proceedings of the 24th International Conference on Field Programmable Logic and Applications (pp. 1-8). IEEE. https://doi.org/10.1109/FPL.2014.6927491

Vancouver

Koch D, Herkersdorf A, (ed.). Hierarchical reconfiguration of FPGAs. In Herkersdorf A, editor, Proceedings of the 24th International Conference on Field Programmable Logic and Applications. USA: IEEE. 2014. p. 1-8 https://doi.org/10.1109/FPL.2014.6927491

Author

Koch, Dirk ; Herkersdorf, Andreas (Editor). / Hierarchical reconfiguration of FPGAs. Proceedings of the 24th International Conference on Field Programmable Logic and Applications. editor / Andreas Herkersdorf. USA : IEEE, 2014. pp. 1-8

Bibtex

@inproceedings{9086365a58394346a91cf71594eeb0bb,
title = "Hierarchical reconfiguration of FPGAs",
abstract = "Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.",
keywords = "Partial Reconfiguration, FPGA Reconfiguration",
author = "Dirk Koch and Andreas Herkersdorf",
year = "2014",
doi = "10.1109/FPL.2014.6927491",
language = "English",
pages = "1--8",
editor = "Andreas Herkersdorf",
booktitle = "Proceedings of the 24th International Conference on Field Programmable Logic and Applications",
publisher = "IEEE",
address = "United States",
note = "Field Programmable Logic and Applications (FPL) ; Conference date: 02-09-2014 Through 04-09-2014",

}

RIS

TY - GEN

T1 - Hierarchical reconfiguration of FPGAs

AU - Koch, Dirk

A2 - Herkersdorf, Andreas

A2 - Herkersdorf, Andreas

PY - 2014

Y1 - 2014

N2 - Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.

AB - Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.

KW - Partial Reconfiguration

KW - FPGA Reconfiguration

U2 - 10.1109/FPL.2014.6927491

DO - 10.1109/FPL.2014.6927491

M3 - Conference contribution

SP - 1

EP - 8

BT - Proceedings of the 24th International Conference on Field Programmable Logic and Applications

PB - IEEE

CY - USA

T2 - Field Programmable Logic and Applications (FPL)

Y2 - 2 September 2014 through 4 September 2014

ER -