Hierarchical reconfiguration of FPGAs

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

  • Authors:
  • Dirk Koch
  • Andreas Herkersdorf (Editor)

Abstract

Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.

Bibliographical metadata

Original languageEnglish
Title of host publicationProceedings of the 24th International Conference on Field Programmable Logic and Applications
EditorsAndreas Herkersdorf
Place of PublicationUSA
PublisherIEEE
Pages1-8
Number of pages8
DOIs
Publication statusPublished - 2014
EventField Programmable Logic and Applications (FPL) - Munich
Event duration: 2 Sep 20144 Sep 2014

Conference

ConferenceField Programmable Logic and Applications (FPL)
CityMunich
Period2/09/144/09/14

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