Future trends in SoC interconnectCitation formats

TY - GEN

T1 - Future trends in SoC interconnect

AU - Furber, Stephen

AU - Bainbridge, John

PY - 2005

Y1 - 2005

N2 - Self-timed packet-switched networks are poised to take a major role in addressing the problems of timing closure power management and overwhelming complexity in the design of Systems-on-Chip. The robust, correct-by-construction characteristics of self-timed communications enables each IP block on the SoC to operate in its own isolated timing domain, greatly simplifying the problems of timing validation. The inherent data-driven nature of the self-timed network, combined with the improved wire segmentation provided by the switched network architecture gives greatly improved power management. Design automation software can remove the need for expertise in self-timed design and networking principles, enabling the on-chip interconnect to be treated as an additional IP block within a conventional (synchronous) design flow. The paradigm shift from viewing the SoC design problem as a matter of organizing complex hierarchies of buses with multiple coupled timing domains, where every interface between timing domains must be verified carefully, to viewing the SoC as a problem in network design where those timing issues are automatically isolated, promises significant improvements in designer productivity, component reuse and SoC functionality.

AB - Self-timed packet-switched networks are poised to take a major role in addressing the problems of timing closure power management and overwhelming complexity in the design of Systems-on-Chip. The robust, correct-by-construction characteristics of self-timed communications enables each IP block on the SoC to operate in its own isolated timing domain, greatly simplifying the problems of timing validation. The inherent data-driven nature of the self-timed network, combined with the improved wire segmentation provided by the switched network architecture gives greatly improved power management. Design automation software can remove the need for expertise in self-timed design and networking principles, enabling the on-chip interconnect to be treated as an additional IP block within a conventional (synchronous) design flow. The paradigm shift from viewing the SoC design problem as a matter of organizing complex hierarchies of buses with multiple coupled timing domains, where every interface between timing domains must be verified carefully, to viewing the SoC as a problem in network design where those timing issues are automatically isolated, promises significant improvements in designer productivity, component reuse and SoC functionality.

UR - http://www.scopus.com/inward/record.url?scp=33847223091&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33847223091

SN - 0780392949

SN - 9780780392946

VL - 2005

SP - 183

EP - 186

BT - 2005 International Symposium on System-on-Chip, Proceedings

T2 - 2005 International Symposium on System-on-Chip

Y2 - 15 November 2005 through 17 November 2005

ER -