Future trends in SoC interconnect

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Self-timed packet-switched networks are poised to take a major role in addressing the problems of timing closure power management and overwhelming complexity in the design of Systems-on-Chip. The robust, correct-by-construction characteristics of self-timed communications enables each IP block on the SoC to operate in its own isolated timing domain, greatly simplifying the problems of timing validation. The inherent data-driven nature of the self-timed network, combined with the improved wire segmentation provided by the switched network architecture gives greatly improved power management. Design automation software can remove the need for expertise in self-timed design and networking principles, enabling the on-chip interconnect to be treated as an additional IP block within a conventional (synchronous) design flow. The paradigm shift from viewing the SoC design problem as a matter of organizing complex hierarchies of buses with multiple coupled timing domains, where every interface between timing domains must be verified carefully, to viewing the SoC as a problem in network design where those timing issues are automatically isolated, promises significant improvements in designer productivity, component reuse and SoC functionality.

Bibliographical metadata

Original languageEnglish
Title of host publication2005 International Symposium on System-on-Chip, Proceedings
Number of pages4
Publication statusPublished - 2005
Event2005 International Symposium on System-on-Chip - Tampere, Finland
Event duration: 15 Nov 200517 Nov 2005


Conference2005 International Symposium on System-on-Chip