FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAsCitation formats

Standard

FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs. / La, Tuan; Mätas, Kaspar; Grunchevski, Nikola; Pham, Khoa; Koch, Dirk.

In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 13, No. 3, 3402937, 02.09.2020.

Research output: Contribution to journalArticlepeer-review

Harvard

La, T, Mätas, K, Grunchevski, N, Pham, K & Koch, D 2020, 'FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs', ACM Transactions on Reconfigurable Technology and Systems, vol. 13, no. 3, 3402937. https://doi.org/10.1145/3402937

APA

La, T., Mätas, K., Grunchevski, N., Pham, K., & Koch, D. (2020). FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs. ACM Transactions on Reconfigurable Technology and Systems, 13(3), [3402937]. https://doi.org/10.1145/3402937

Vancouver

La T, Mätas K, Grunchevski N, Pham K, Koch D. FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs. ACM Transactions on Reconfigurable Technology and Systems. 2020 Sep 2;13(3). 3402937. https://doi.org/10.1145/3402937

Author

La, Tuan ; Mätas, Kaspar ; Grunchevski, Nikola ; Pham, Khoa ; Koch, Dirk. / FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs. In: ACM Transactions on Reconfigurable Technology and Systems. 2020 ; Vol. 13, No. 3.

Bibtex

@article{f2a706d8c6d44622adbdfa039f18a1a0,
title = "FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs",
abstract = "Sharing configuration bitstreams rather than netlists is a very desirable feature to protect IP or to share IP without longer CAD tool processing times. Furthermore, an increasing number of systems could hugely benefit from serving multiple users on the same FPGA, for example, for resource pooling in cloud infrastructures. This paper researches the threat that a malicious application can impose on an FPGA based system in a multi-tenancy scenario from a hardware security point of view. In particular, this paper evaluates the risk systematically for FPGA power-hammering through short-circuits and self-oscillating circuits which potentially may cause harm to a system. This risk includes implementing, tuning, and evaluating all FPGA self-oscillators known from the literature, but also, developing a large number of new power-hammering designs which have not been considered before. Our experiments demonstrate that malicious circuits can be tuned to the point that just 3% of the logic available on an Ultra96 FPGA board can draw the power budget of the entire FPGA board. This fact suggests a waste power potential for datacenter FPGAs in the range of kilowatts.In addition to carefully analyzing FPGA hardware security threats, we present the FPGA virus scanner FPGADefender that can detect (possibly) any self-oscillating FPGA circuit, as well as detecting short-circuits, high fanout nets, and a tapping onto signals outside the scope of a module for protecting data center FPGAs such as Xilinx UltraScale+ devices at the bitstream level.",
keywords = "Cloud computing, FPGA, bitstream, countermeasure, denial-of-service, hardware security, mitigation, power-hammering, side-channel",
author = "Tuan La and Kaspar M{\"a}tas and Nikola Grunchevski and Khoa Pham and Dirk Koch",
note = "Funding Information: This work is kindly supported by the UK National Cyber Security Centre through the project rFAS (Grant Agreement No. 4212204/RFA 15971) and by the European Commission through the project EuroEXA (Grant No. 754337). Authors{\textquoteright} addresses: T. M. La, K. Matas, N. Grunchevski, K. D. Pham, and D. Koch, Advanced Processor Technologies Research Group, Information Technology Building, Department of Computer Science, The University of Manchester, Oxford Rd, Manchester M13 9PL, UK; emails: tuan.la@postgrad.manchester.ac.uk, {kaspar.matas, nikola.grunchevski, khoa.pham, dirk.koch}@manchester.ac.uk. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. {\textcopyright} 2020 Association for Computing Machinery. 1936-7406/2020/09-ART15 $15.00 https://doi.org/10.1145/3402937 Publisher Copyright: {\textcopyright} 2020 ACM. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.",
year = "2020",
month = sep,
day = "2",
doi = "10.1145/3402937",
language = "English",
volume = "13",
journal = "ACM Transactions on Reconfigurable Technology and Systems",
issn = "1936-7406",
publisher = "ACM Special Interest Group",
number = "3",

}

RIS

TY - JOUR

T1 - FPGADefender: Malicious Self-Oscillator Scanning for Xilinx UltraScale+ FPGAs

AU - La, Tuan

AU - Mätas, Kaspar

AU - Grunchevski, Nikola

AU - Pham, Khoa

AU - Koch, Dirk

N1 - Funding Information: This work is kindly supported by the UK National Cyber Security Centre through the project rFAS (Grant Agreement No. 4212204/RFA 15971) and by the European Commission through the project EuroEXA (Grant No. 754337). Authors’ addresses: T. M. La, K. Matas, N. Grunchevski, K. D. Pham, and D. Koch, Advanced Processor Technologies Research Group, Information Technology Building, Department of Computer Science, The University of Manchester, Oxford Rd, Manchester M13 9PL, UK; emails: tuan.la@postgrad.manchester.ac.uk, {kaspar.matas, nikola.grunchevski, khoa.pham, dirk.koch}@manchester.ac.uk. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2020 Association for Computing Machinery. 1936-7406/2020/09-ART15 $15.00 https://doi.org/10.1145/3402937 Publisher Copyright: © 2020 ACM. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.

PY - 2020/9/2

Y1 - 2020/9/2

N2 - Sharing configuration bitstreams rather than netlists is a very desirable feature to protect IP or to share IP without longer CAD tool processing times. Furthermore, an increasing number of systems could hugely benefit from serving multiple users on the same FPGA, for example, for resource pooling in cloud infrastructures. This paper researches the threat that a malicious application can impose on an FPGA based system in a multi-tenancy scenario from a hardware security point of view. In particular, this paper evaluates the risk systematically for FPGA power-hammering through short-circuits and self-oscillating circuits which potentially may cause harm to a system. This risk includes implementing, tuning, and evaluating all FPGA self-oscillators known from the literature, but also, developing a large number of new power-hammering designs which have not been considered before. Our experiments demonstrate that malicious circuits can be tuned to the point that just 3% of the logic available on an Ultra96 FPGA board can draw the power budget of the entire FPGA board. This fact suggests a waste power potential for datacenter FPGAs in the range of kilowatts.In addition to carefully analyzing FPGA hardware security threats, we present the FPGA virus scanner FPGADefender that can detect (possibly) any self-oscillating FPGA circuit, as well as detecting short-circuits, high fanout nets, and a tapping onto signals outside the scope of a module for protecting data center FPGAs such as Xilinx UltraScale+ devices at the bitstream level.

AB - Sharing configuration bitstreams rather than netlists is a very desirable feature to protect IP or to share IP without longer CAD tool processing times. Furthermore, an increasing number of systems could hugely benefit from serving multiple users on the same FPGA, for example, for resource pooling in cloud infrastructures. This paper researches the threat that a malicious application can impose on an FPGA based system in a multi-tenancy scenario from a hardware security point of view. In particular, this paper evaluates the risk systematically for FPGA power-hammering through short-circuits and self-oscillating circuits which potentially may cause harm to a system. This risk includes implementing, tuning, and evaluating all FPGA self-oscillators known from the literature, but also, developing a large number of new power-hammering designs which have not been considered before. Our experiments demonstrate that malicious circuits can be tuned to the point that just 3% of the logic available on an Ultra96 FPGA board can draw the power budget of the entire FPGA board. This fact suggests a waste power potential for datacenter FPGAs in the range of kilowatts.In addition to carefully analyzing FPGA hardware security threats, we present the FPGA virus scanner FPGADefender that can detect (possibly) any self-oscillating FPGA circuit, as well as detecting short-circuits, high fanout nets, and a tapping onto signals outside the scope of a module for protecting data center FPGAs such as Xilinx UltraScale+ devices at the bitstream level.

KW - Cloud computing

KW - FPGA

KW - bitstream

KW - countermeasure

KW - denial-of-service

KW - hardware security

KW - mitigation

KW - power-hammering

KW - side-channel

UR - http://www.scopus.com/inward/record.url?scp=85091045808&partnerID=8YFLogxK

U2 - 10.1145/3402937

DO - 10.1145/3402937

M3 - Article

VL - 13

JO - ACM Transactions on Reconfigurable Technology and Systems

JF - ACM Transactions on Reconfigurable Technology and Systems

SN - 1936-7406

IS - 3

M1 - 3402937

ER -