FastPath: Towards Wire-speed NVMe SSDs

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The constant growth of data and its importance to drive Machine Learning and Big Data is pushing storage systems towards ever increasing I/O bandwidth and lower latency requirements.
In recent years, the Non Volatile Memory Express (NVMe) standard has enabled SSD drives to deliver high I/O rates by allowing the storage to be connected directly via the fastest available interconnect to the processing chip.
In parallel, the adoption of FPGAs in data centers is creating opportunities to accelerate various applications and/or Operating System (OS) operations. While, FPGAs in data centers have been connected via PCIe to mostly x86 servers, we have now also available heterogeneous SoCs with multi-cores and FPGAs integrated on the same die and connected by an on-chip interconnect.

In this paper, we present how to rethink and accelerate NVMe performance on heterogeneous SoC with integrated FPGAs providing a first research insight on the performance benefits of such an approach.
We provide an analysis of the Linux block I/O layer and showcase the relationship between the system's performance and its I/O implementation.
Consequently, we introduce an FPGA-based fast path which accelerates the access to the NVMe drive.
Our comparative evaluation demonstrates that our FPGA-based FastPath achieves up to 71% lower latency
and up to 5x higher I/O performance against the baseline system on a Zynq development board.

Bibliographical metadata

Original languageEnglish
Title of host publication2018 28th International Conference on Field Programmable Logic and Applications (FPL)
PublisherIEEE
Number of pages8
DOIs
Publication statusPublished - 6 Dec 2018

Publication series

Name2018 28th International Conference on Field Programmable Logic and Applications (FPL)
PublisherIEEE
ISSN (Print)1946-147X
ISSN (Electronic)1946-1488

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