Event-driven MLP implementation on neuromimetic hardwareCitation formats

Standard

Event-driven MLP implementation on neuromimetic hardware. / Rast, A. D.; Plana, Luis A.; Welbourne, S. R.; Furber, S. B.

Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE Computer Society , 2012.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Rast, AD, Plana, LA, Welbourne, SR & Furber, SB 2012, Event-driven MLP implementation on neuromimetic hardware. in Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE Computer Society , 2012 Annual International Joint Conference on Neural Networks, IJCNN 2012, Part of the 2012 IEEE World Congress on Computational Intelligence, WCCI 2012, Brisbane, QLD, 1/07/12. https://doi.org/10.1109/IJCNN.2012.6252821

APA

Rast, A. D., Plana, L. A., Welbourne, S. R., & Furber, S. B. (2012). Event-driven MLP implementation on neuromimetic hardware. In Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks IEEE Computer Society . https://doi.org/10.1109/IJCNN.2012.6252821

Vancouver

Rast AD, Plana LA, Welbourne SR, Furber SB. Event-driven MLP implementation on neuromimetic hardware. In Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE Computer Society . 2012 https://doi.org/10.1109/IJCNN.2012.6252821

Author

Rast, A. D. ; Plana, Luis A. ; Welbourne, S. R. ; Furber, S. B. / Event-driven MLP implementation on neuromimetic hardware. Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks. IEEE Computer Society , 2012.

Bibtex

@inproceedings{d1be36f77dbd43fd9faf28e332b9c0e2,
title = "Event-driven MLP implementation on neuromimetic hardware",
abstract = "While new neural hardware is increasingly emphasizing spiking neural models, there will still be a need to model classical neural networks like the multilayer perceptron (MLP) for the foreseeable future. Given that the trend in new chips is towards a {"}neuromimetic{"} design that specialises the hardware for neural networks but does not hardwire the model, it is worth examining whether it is possible to implement the MLP on such hardware and realise performance gains over conventional simulation on general- purpose computers. Using the SpiNNaker chip as a demonstration platform, we show that it is possible to find efficient mappings to improve both the performance and the scalability of the MLP network, allowing for much larger models than possible in software. These mappings, however require a careful consideration of how to transform the {"}timeless{"} MLP model into an event-driven implementation. Examination of the hardware performance also reveals the importance of distributing processing and traffic load so that local congestion does not end up crippling the simulation. These considerations being solved, not only does the hardware demonstrate the potential for significant performance improvement, it also illustrates important general techniques and methods for translating nonspiking models onto the emerging generation of spiking neural hardware. The results suggest both the form that models might take and the architectures that future neural hardware could adopt for optimum generality and performance. {\textcopyright} 2012 IEEE.",
keywords = "MLP;SpiNNaker chip;SpiNNaker software architecture;event-driven implementation;event-driven multilayer perceptron;general-purpose computer;neural network;neuromimetic design;, neuromimetic hardware;nonspiking model;spiking neural hardware",
author = "Rast, {A. D.} and Plana, {Luis A.} and Welbourne, {S. R.} and Furber, {S. B.}",
year = "2012",
doi = "10.1109/IJCNN.2012.6252821",
language = "English",
isbn = "9781467314909",
booktitle = "Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks",
publisher = "IEEE Computer Society ",
address = "United States",
note = "2012 Annual International Joint Conference on Neural Networks, IJCNN 2012, Part of the 2012 IEEE World Congress on Computational Intelligence, WCCI 2012 ; Conference date: 01-07-2012",

}

RIS

TY - GEN

T1 - Event-driven MLP implementation on neuromimetic hardware

AU - Rast, A. D.

AU - Plana, Luis A.

AU - Welbourne, S. R.

AU - Furber, S. B.

PY - 2012

Y1 - 2012

N2 - While new neural hardware is increasingly emphasizing spiking neural models, there will still be a need to model classical neural networks like the multilayer perceptron (MLP) for the foreseeable future. Given that the trend in new chips is towards a "neuromimetic" design that specialises the hardware for neural networks but does not hardwire the model, it is worth examining whether it is possible to implement the MLP on such hardware and realise performance gains over conventional simulation on general- purpose computers. Using the SpiNNaker chip as a demonstration platform, we show that it is possible to find efficient mappings to improve both the performance and the scalability of the MLP network, allowing for much larger models than possible in software. These mappings, however require a careful consideration of how to transform the "timeless" MLP model into an event-driven implementation. Examination of the hardware performance also reveals the importance of distributing processing and traffic load so that local congestion does not end up crippling the simulation. These considerations being solved, not only does the hardware demonstrate the potential for significant performance improvement, it also illustrates important general techniques and methods for translating nonspiking models onto the emerging generation of spiking neural hardware. The results suggest both the form that models might take and the architectures that future neural hardware could adopt for optimum generality and performance. © 2012 IEEE.

AB - While new neural hardware is increasingly emphasizing spiking neural models, there will still be a need to model classical neural networks like the multilayer perceptron (MLP) for the foreseeable future. Given that the trend in new chips is towards a "neuromimetic" design that specialises the hardware for neural networks but does not hardwire the model, it is worth examining whether it is possible to implement the MLP on such hardware and realise performance gains over conventional simulation on general- purpose computers. Using the SpiNNaker chip as a demonstration platform, we show that it is possible to find efficient mappings to improve both the performance and the scalability of the MLP network, allowing for much larger models than possible in software. These mappings, however require a careful consideration of how to transform the "timeless" MLP model into an event-driven implementation. Examination of the hardware performance also reveals the importance of distributing processing and traffic load so that local congestion does not end up crippling the simulation. These considerations being solved, not only does the hardware demonstrate the potential for significant performance improvement, it also illustrates important general techniques and methods for translating nonspiking models onto the emerging generation of spiking neural hardware. The results suggest both the form that models might take and the architectures that future neural hardware could adopt for optimum generality and performance. © 2012 IEEE.

KW - MLP;SpiNNaker chip;SpiNNaker software architecture;event-driven implementation;event-driven multilayer perceptron;general-purpose computer;neural network;neuromimetic design;

KW - neuromimetic hardware;nonspiking model;spiking neural hardware

U2 - 10.1109/IJCNN.2012.6252821

DO - 10.1109/IJCNN.2012.6252821

M3 - Conference contribution

SN - 9781467314909

BT - Proceedings of the International Joint Conference on Neural Networks|Proc Int Jt Conf Neural Networks

PB - IEEE Computer Society

T2 - 2012 Annual International Joint Conference on Neural Networks, IJCNN 2012, Part of the 2012 IEEE World Congress on Computational Intelligence, WCCI 2012

Y2 - 1 July 2012

ER -