Dynamic Voltage and Frequency Scaling is the most commonly used power management technique in modern processors. However, the ability of an individual chip to operate under reduced supply voltage can no longer be predetermined at the design stage and may even change over time. This paper presents a dynamic power-management strategy for out-of-order CPUs using Cyclic Power Gating (CPG). CPG is an aggressive power-gating strategy where the CPU is powered on and off again at high frequency allowing the fine-grained control of frequency and power consumption without scaling the supply voltage. A key challenge with power-gating out-of-order CPUs is the serialization of memory accesses. The paper presents CRIT
CPG a low-cost method to accurately predict serialized memory accesses that allows the impact of power-gating on performance to be determined. CRIT
CPG is employed within a hardware governor that adapts the power-gating to CPU execution phases. Detailed simulations of the governor are carried out over a range of benchmarks, the CPG governor shows on average an 11% reduction in energy consumption and an 8% increase in energy efficiency over a state-of-the-art DVFS governor. Using these techniques, not only can CPG provide fine-grained power consumption control to rival DVFS, but it can also be used alongside DVFS to further increase the energy-efficiency of CPUs.