Efficient microarchitecture policies for accurately adapting to power constraintsCitation formats

  • Authors:
  • Juan M. Cebrián
  • Juan L. Aragón
  • José M. García
  • Pavlos Petoumenos
  • Stefanos Kaxiras

Standard

Efficient microarchitecture policies for accurately adapting to power constraints. / Cebrián, Juan M.; Aragón, Juan L.; García, José M.; Petoumenos, Pavlos; Kaxiras, Stefanos.

IPDPS 2009 Rome: Proceedings of the 2009 IEEE International Parallel & Distributed Processing Symposium . IEEE, 2009. 5161022.

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Harvard

Cebrián, JM, Aragón, JL, García, JM, Petoumenos, P & Kaxiras, S 2009, Efficient microarchitecture policies for accurately adapting to power constraints. in IPDPS 2009 Rome: Proceedings of the 2009 IEEE International Parallel & Distributed Processing Symposium ., 5161022, IEEE, 23rd IEEE International Parallel and Distributed Processing Symposium, Rome, Italy, 23/05/09. https://doi.org/10.1109/IPDPS.2009.5161022

APA

Cebrián, J. M., Aragón, J. L., García, J. M., Petoumenos, P., & Kaxiras, S. (2009). Efficient microarchitecture policies for accurately adapting to power constraints. In IPDPS 2009 Rome: Proceedings of the 2009 IEEE International Parallel & Distributed Processing Symposium  [5161022] IEEE. https://doi.org/10.1109/IPDPS.2009.5161022

Vancouver

Cebrián JM, Aragón JL, García JM, Petoumenos P, Kaxiras S. Efficient microarchitecture policies for accurately adapting to power constraints. In IPDPS 2009 Rome: Proceedings of the 2009 IEEE International Parallel & Distributed Processing Symposium . IEEE. 2009. 5161022 https://doi.org/10.1109/IPDPS.2009.5161022

Author

Cebrián, Juan M. ; Aragón, Juan L. ; García, José M. ; Petoumenos, Pavlos ; Kaxiras, Stefanos. / Efficient microarchitecture policies for accurately adapting to power constraints. IPDPS 2009 Rome: Proceedings of the 2009 IEEE International Parallel & Distributed Processing Symposium . IEEE, 2009.

Bibtex

@inproceedings{22d31bfd8e3049c48e834d125dceab60,
title = "Efficient microarchitecture policies for accurately adapting to power constraints",
abstract = "In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won't be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving microarchitectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed (area) over the power budget, than using DVFS alone for matching a predefined power budget. Furthermore, in a near future DVFS will become DFS because lowering the supply voltage will be too expensive in terms of leakage power. At that point, the use of power-saving microarchitectural techniques will become even more energy efficient.",
author = "Cebri{\'a}n, {Juan M.} and Arag{\'o}n, {Juan L.} and Garc{\'i}a, {Jos{\'e} M.} and Pavlos Petoumenos and Stefanos Kaxiras",
year = "2009",
month = nov,
day = "25",
doi = "10.1109/IPDPS.2009.5161022",
language = "English",
isbn = "9781424437504",
booktitle = "IPDPS 2009 Rome",
publisher = "IEEE",
address = "United States",
note = "23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009 ; Conference date: 23-05-2009 Through 29-05-2009",

}

RIS

TY - GEN

T1 - Efficient microarchitecture policies for accurately adapting to power constraints

AU - Cebrián, Juan M.

AU - Aragón, Juan L.

AU - García, José M.

AU - Petoumenos, Pavlos

AU - Kaxiras, Stefanos

PY - 2009/11/25

Y1 - 2009/11/25

N2 - In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won't be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving microarchitectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed (area) over the power budget, than using DVFS alone for matching a predefined power budget. Furthermore, in a near future DVFS will become DFS because lowering the supply voltage will be too expensive in terms of leakage power. At that point, the use of power-saving microarchitectural techniques will become even more energy efficient.

AB - In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won't be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving microarchitectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed (area) over the power budget, than using DVFS alone for matching a predefined power budget. Furthermore, in a near future DVFS will become DFS because lowering the supply voltage will be too expensive in terms of leakage power. At that point, the use of power-saving microarchitectural techniques will become even more energy efficient.

UR - http://www.scopus.com/inward/record.url?scp=70450091396&partnerID=8YFLogxK

U2 - 10.1109/IPDPS.2009.5161022

DO - 10.1109/IPDPS.2009.5161022

M3 - Conference contribution

AN - SCOPUS:70450091396

SN - 9781424437504

BT - IPDPS 2009 Rome

PB - IEEE

T2 - 23rd IEEE International Parallel and Distributed Processing Symposium

Y2 - 23 May 2009 through 29 May 2009

ER -