Efficient microarchitecture policies for accurately adapting to power constraints

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  • Authors:
  • Juan M. Cebrián
  • Juan L. Aragón
  • José M. García
  • Pavlos Petoumenos
  • Stefanos Kaxiras

Abstract

In the past years Dynamic Voltage and Frequency Scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won't be useful at all (when static power exceeds dynamic power). In this paper we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy efficiency of the processor. We will predict the processor power consumption at a basic block level, using the consumed power translated into tokens to select between different power-saving microarchitectural techniques. These techniques are orthogonal to DVFS so they can be simultaneously applied. We propose a two-level approach where DVFS acts as a coarse-grained technique to lower the average power while microarchitectural techniques remove all the power spikes efficiently. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed (area) over the power budget, than using DVFS alone for matching a predefined power budget. Furthermore, in a near future DVFS will become DFS because lowering the supply voltage will be too expensive in terms of leakage power. At that point, the use of power-saving microarchitectural techniques will become even more energy efficient.

Bibliographical metadata

Original languageEnglish
Title of host publicationIPDPS 2009 Rome
Subtitle of host publicationProceedings of the 2009 IEEE International Parallel & Distributed Processing Symposium 
PublisherIEEE
Number of pages12
ISBN (Print)9781424437504
DOIs
Publication statusPublished - 25 Nov 2009
Event23rd IEEE International Parallel and Distributed Processing Symposium - Rome, Italy
Event duration: 23 May 200929 May 2009

Conference

Conference23rd IEEE International Parallel and Distributed Processing Symposium
Abbreviated titleIPDPS 2009
CountryItaly
CityRome
Period23/05/0929/05/09