Dynamic Power Management for Neuromorphic Many-Core Systems

Research output: Contribution to journalArticle

  • External authors:
  • Sebastian Hoppner
  • Bernhard Vogginger
  • Yexin Yan
  • Andreas Dixius
  • Stefan Scholze
  • Johannes Partzsch
  • Felix Neumärker
  • Stephan Hartmann
  • Stefan Schiefer
  • Georg Ellguth
  • Love Cederstroem
  • Christian Mayr

Abstract

This paper presents a dynamic power management architecture for neuromorphic many-core systems, such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PEs) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28-nm SLP CMOS technology has been implemented. It includes four PEs which can be scaled from 0.7 to 1.0 V with frequencies from 125 to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks, it is shown that the total PE power consumption can be reduced by 75%, with 80% baseline power reduction and a 50% reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second-generation SpiNNaker neuromorphic many-core system.

Bibliographical metadata

Original languageEnglish
Pages (from-to)2973-2986
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume66
Issue number8
Early online date29 Apr 2019
DOIs
Publication statusPublished - 2019