Designing robust asynchronous circuit componentsCitation formats

Standard

Designing robust asynchronous circuit components. / Mohammadi, S.; Furber, S.; Garside, J.

In: IEE Proceedings: Circuits, Devices and Systems, Vol. 150, No. 3, 06.2003, p. 161-166.

Research output: Contribution to journalArticlepeer-review

Harvard

Mohammadi, S, Furber, S & Garside, J 2003, 'Designing robust asynchronous circuit components', IEE Proceedings: Circuits, Devices and Systems, vol. 150, no. 3, pp. 161-166. https://doi.org/10.1049/ip-cds:20030349

APA

Mohammadi, S., Furber, S., & Garside, J. (2003). Designing robust asynchronous circuit components. IEE Proceedings: Circuits, Devices and Systems, 150(3), 161-166. https://doi.org/10.1049/ip-cds:20030349

Vancouver

Mohammadi S, Furber S, Garside J. Designing robust asynchronous circuit components. IEE Proceedings: Circuits, Devices and Systems. 2003 Jun;150(3):161-166. https://doi.org/10.1049/ip-cds:20030349

Author

Mohammadi, S. ; Furber, S. ; Garside, J. / Designing robust asynchronous circuit components. In: IEE Proceedings: Circuits, Devices and Systems. 2003 ; Vol. 150, No. 3. pp. 161-166.

Bibtex

@article{7ebd35dcef6648d48b854f8c7ba40c09,
title = "Designing robust asynchronous circuit components",
abstract = "Asynchronous circuits require components that display hazard-free operation under normal input conditions. In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example, dynamic or pseudo-dynamic C-gate circuits. In the paper, the authors investigate the severity of these problems in practical circuits. It is shown that threshold variations are much less significant than has previously been assumed, but hazard-free operation is, by contrast, a much more significant problem. Gates with a stack of transistors in series can exhibit charge-sharing problems under specific input sequences that expose hazards that are not evident in the logic description. A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits.",
author = "S. Mohammadi and S. Furber and J. Garside",
year = "2003",
month = jun,
doi = "10.1049/ip-cds:20030349",
language = "English",
volume = "150",
pages = "161--166",
journal = "IEE Proceedings: Circuits, Devices and Systems",
issn = "1350-2409",
publisher = "IEE",
number = "3",

}

RIS

TY - JOUR

T1 - Designing robust asynchronous circuit components

AU - Mohammadi, S.

AU - Furber, S.

AU - Garside, J.

PY - 2003/6

Y1 - 2003/6

N2 - Asynchronous circuits require components that display hazard-free operation under normal input conditions. In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example, dynamic or pseudo-dynamic C-gate circuits. In the paper, the authors investigate the severity of these problems in practical circuits. It is shown that threshold variations are much less significant than has previously been assumed, but hazard-free operation is, by contrast, a much more significant problem. Gates with a stack of transistors in series can exhibit charge-sharing problems under specific input sequences that expose hazards that are not evident in the logic description. A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits.

AB - Asynchronous circuits require components that display hazard-free operation under normal input conditions. In addition, quasi-delay-insensitive circuits are based on the assumption of isochronic forks, an assumption that can in practice be compromised by threshold variations due to the use of, for example, dynamic or pseudo-dynamic C-gate circuits. In the paper, the authors investigate the severity of these problems in practical circuits. It is shown that threshold variations are much less significant than has previously been assumed, but hazard-free operation is, by contrast, a much more significant problem. Gates with a stack of transistors in series can exhibit charge-sharing problems under specific input sequences that expose hazards that are not evident in the logic description. A design methodology is proposed which overcomes the charge-sharing problem, resulting in more robust circuits.

U2 - 10.1049/ip-cds:20030349

DO - 10.1049/ip-cds:20030349

M3 - Article

VL - 150

SP - 161

EP - 166

JO - IEE Proceedings: Circuits, Devices and Systems

JF - IEE Proceedings: Circuits, Devices and Systems

SN - 1350-2409

IS - 3

ER -