Designing asynchronous sequential circuits for random pattern testabilityCitation formats

  • Authors:
  • O. A. Petlin
  • S. B. Furber
  • A. M. Romankevich
  • V. V. Groll

Standard

Designing asynchronous sequential circuits for random pattern testability. / Petlin, O. A.; Furber, S. B.; Romankevich, A. M.; Groll, V. V.

In: IEE Proceedings: Computers and Digital Techniques, Vol. 142, No. 4, 07.1995, p. 299-305.

Research output: Contribution to journalArticlepeer-review

Harvard

Petlin, OA, Furber, SB, Romankevich, AM & Groll, VV 1995, 'Designing asynchronous sequential circuits for random pattern testability', IEE Proceedings: Computers and Digital Techniques, vol. 142, no. 4, pp. 299-305. https://doi.org/10.1049/ip-cdt:19951982

APA

Petlin, O. A., Furber, S. B., Romankevich, A. M., & Groll, V. V. (1995). Designing asynchronous sequential circuits for random pattern testability. IEE Proceedings: Computers and Digital Techniques, 142(4), 299-305. https://doi.org/10.1049/ip-cdt:19951982

Vancouver

Petlin OA, Furber SB, Romankevich AM, Groll VV. Designing asynchronous sequential circuits for random pattern testability. IEE Proceedings: Computers and Digital Techniques. 1995 Jul;142(4):299-305. https://doi.org/10.1049/ip-cdt:19951982

Author

Petlin, O. A. ; Furber, S. B. ; Romankevich, A. M. ; Groll, V. V. / Designing asynchronous sequential circuits for random pattern testability. In: IEE Proceedings: Computers and Digital Techniques. 1995 ; Vol. 142, No. 4. pp. 299-305.

Bibtex

@article{c24e736ef9ef4de0b6b5c7b91b853f6e,
title = "Designing asynchronous sequential circuits for random pattern testability",
abstract = "A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential circuits provides for the separate testing of the combinational logic block and the memory elements. The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic block. A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach.",
author = "Petlin, {O. A.} and Furber, {S. B.} and Romankevich, {A. M.} and Groll, {V. V.}",
year = "1995",
month = jul,
doi = "10.1049/ip-cdt:19951982",
language = "English",
volume = "142",
pages = "299--305",
journal = "IEE Proceedings: Computers and Digital Techniques",
issn = "1350-2387",
publisher = "IEE",
number = "4",

}

RIS

TY - JOUR

T1 - Designing asynchronous sequential circuits for random pattern testability

AU - Petlin, O. A.

AU - Furber, S. B.

AU - Romankevich, A. M.

AU - Groll, V. V.

PY - 1995/7

Y1 - 1995/7

N2 - A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential circuits provides for the separate testing of the combinational logic block and the memory elements. The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic block. A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach.

AB - A resurgence of interest in asynchronous VLSI circuits is occurring because of their potential for low power consumption, design flexibility and the absence of the clock skew problem. In this paper, an approach to the design of asynchronous sequential circuits for random pattern testability based on the micropipeline design style is described. The test procedure for such asynchronous sequential circuits provides for the separate testing of the combinational logic block and the memory elements. The total number of random test patterns required to detect all the stuck-at faults in the data processing blocks and control blocks is determined by the total number of tests for the combinational logic block. A case study of a register destination decoder designed for random pattern testability is presented to demonstrate the practicability of the proposed design approach.

UR - http://www.scopus.com/inward/record.url?scp=0029344335&partnerID=8YFLogxK

U2 - 10.1049/ip-cdt:19951982

DO - 10.1049/ip-cdt:19951982

M3 - Article

AN - SCOPUS:0029344335

VL - 142

SP - 299

EP - 305

JO - IEE Proceedings: Computers and Digital Techniques

JF - IEE Proceedings: Computers and Digital Techniques

SN - 1350-2387

IS - 4

ER -