Delay insensitive system-on-chip interconnect using 1-of-4 data encoding

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The demands of System-on-Chip (SoC) interconnect increasingly cannot be satisfied through the use of a shared bus. A common alternative, using unidirectional, point-to-point connections and multiplexers, results in much greater area requirements and still suffers from some of the same problems. This paper introduces a delay-insensitive, asynchronous approach to interconnect over long paths using 1-of-4 encoded channels switched through multiplexers. A re-implementation of the MARBLE SoC bus (as used in the AMULET3H chip) using this technique shows that it can provide a higher throughput than the simpler tristate bus while using a narrower datapath. © 2001 IEEE.

Bibliographical metadata

Original languageEnglish
Title of host publicationProceedings - International Symposium on Asynchronous Circuits and Systems|Proc. Int. Symp. Asynchr. Circuits Syst.
PublisherIEEE Computer Society
Pages118-126
Number of pages8
DOIs
Publication statusPublished - 2001
Event7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001 - Salt Lake City, UT
Event duration: 1 Jul 2001 → …
http://dblp.uni-trier.de/db/conf/async/async2001.html#BainbridgeF01http://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01.xmlhttp://dblp.uni-trier.de/rec/bibtex/conf/async/BainbridgeF01

Conference

Conference7th International Symposium on Asynchronous Circuits and Systems, ASYNC 2001
CitySalt Lake City, UT
Period1/07/01 → …
Internet address