Correct and efficient bounded FIFO queuesCitation formats
Standard
Correct and efficient bounded FIFO queues. / Lê, Nhat Minh; Guatto, Adrien; Cohen, Albert; Pop, Antoniu.
Proceedings - Symposium on Computer Architecture and High Performance Computing|Proc. Symp. Comput. Archit. High Perform. Comput.. IEEE Computer Society , 2013. p. 144-151.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review
Harvard
APA
Vancouver
Author
Bibtex
}
RIS
TY - GEN
T1 - Correct and efficient bounded FIFO queues
AU - Lê, Nhat Minh
AU - Guatto, Adrien
AU - Cohen, Albert
AU - Pop, Antoniu
PY - 2013
Y1 - 2013
N2 - Bounded single-producer single-consumer FIFO queues are one of the simplest concurrent data-structure, and they do not require more than sequential consistency for correct operation. Still, sequential consistency is an unrealistic hypothesis on shared-memory multiprocessors, and enforcing it through memory barriers induces significant performance and energy overhead. This paper revisits the optimization and correctness proof of bounded FIFO queues in the context of weak memory consistency, building upon the recent axiomatic formalization of the C11 memory model. We validate the portability and performance of our proven implementation over 3 processor architectures with diverse hardware memory models, including ARM and PowerPC. Comparison with state-of-the-art implementations demonstrate consistent improvements for a wide range of buffer and batch sizes. © 2013 IEEE.
AB - Bounded single-producer single-consumer FIFO queues are one of the simplest concurrent data-structure, and they do not require more than sequential consistency for correct operation. Still, sequential consistency is an unrealistic hypothesis on shared-memory multiprocessors, and enforcing it through memory barriers induces significant performance and energy overhead. This paper revisits the optimization and correctness proof of bounded FIFO queues in the context of weak memory consistency, building upon the recent axiomatic formalization of the C11 memory model. We validate the portability and performance of our proven implementation over 3 processor architectures with diverse hardware memory models, including ARM and PowerPC. Comparison with state-of-the-art implementations demonstrate consistent improvements for a wide range of buffer and batch sizes. © 2013 IEEE.
KW - Data-flow programming
KW - FIFO queue
KW - Kahn process network
KW - Lock-free algorithm
KW - Weak memory model
U2 - 10.1109/SBAC-PAD.2013.8
DO - 10.1109/SBAC-PAD.2013.8
M3 - Conference contribution
SN - 9781479929276
SP - 144
EP - 151
BT - Proceedings - Symposium on Computer Architecture and High Performance Computing|Proc. Symp. Comput. Archit. High Perform. Comput.
PB - IEEE Computer Society
T2 - 2013 25th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2013
Y2 - 1 July 2013
ER -