Asynchronous cellular logic network as a co-processor for a general-purpose massively parallel array

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Abstract

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low-power consumption. An integrated circuit with proof-of-concept array of 24× 60 cells has been fabricated in a 0.35μm three-metal CMOS process and tested. Occupying only 16× 8μm2 the binary wave-propagation cell is designed to be used as a co-processor in general-purpose processor-per-pixel arrays intended for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.

Bibliographical metadata

Original languageEnglish
Pages (from-to)963-972
Number of pages9
JournalInternational Journal of Circuit Theory and Applications
Volume39
Issue number9
DOIs
Publication statusPublished - Sep 2011