Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic ChipCitation formats

  • External authors:
  • Delong Shang
  • Stefan Scholze
  • Sebastian Hoppner
  • Andreas Dixius

Standard

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. / Mikaitis, Mantas; Lester, David; Shang, Delong; Furber, Stephen; Liu, Gengting; Garside, James; Scholze, Stefan; Hoppner, Sebastian; Dixius, Andreas.

2018. 37-44 Paper presented at 25th IEEE Symposium on Computer Arithmetic, .

Research output: Contribution to conferencePaperpeer-review

Harvard

Mikaitis, M, Lester, D, Shang, D, Furber, S, Liu, G, Garside, J, Scholze, S, Hoppner, S & Dixius, A 2018, 'Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip', Paper presented at 25th IEEE Symposium on Computer Arithmetic, 25/06/18 - 27/06/18 pp. 37-44. https://doi.org/10.1109/ARITH.2018.8464785

APA

Mikaitis, M., Lester, D., Shang, D., Furber, S., Liu, G., Garside, J., Scholze, S., Hoppner, S., & Dixius, A. (2018). Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. 37-44. Paper presented at 25th IEEE Symposium on Computer Arithmetic, . https://doi.org/10.1109/ARITH.2018.8464785

Vancouver

Author

Mikaitis, Mantas ; Lester, David ; Shang, Delong ; Furber, Stephen ; Liu, Gengting ; Garside, James ; Scholze, Stefan ; Hoppner, Sebastian ; Dixius, Andreas. / Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip. Paper presented at 25th IEEE Symposium on Computer Arithmetic, .8 p.

Bibtex

@conference{bf3c8125f1734c5b97dbdb10783aee8f,
title = "Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip",
abstract = "Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more e^x components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.",
keywords = "exponential function, logarithm function, hardware accelerators, approximate arithmetic, fixed-point arithmetic, SpiNNaker2, neuromorphic computing, MPSoC",
author = "Mantas Mikaitis and David Lester and Delong Shang and Stephen Furber and Gengting Liu and James Garside and Stefan Scholze and Sebastian Hoppner and Andreas Dixius",
year = "2018",
month = sep,
day = "17",
doi = "10.1109/ARITH.2018.8464785",
language = "English",
pages = "37--44",
note = "25th IEEE Symposium on Computer Arithmetic, ARITH25 ; Conference date: 25-06-2018 Through 27-06-2018",
url = "http://www.ecs.umass.edu/arith-2018/",

}

RIS

TY - CONF

T1 - Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip

AU - Mikaitis, Mantas

AU - Lester, David

AU - Shang, Delong

AU - Furber, Stephen

AU - Liu, Gengting

AU - Garside, James

AU - Scholze, Stefan

AU - Hoppner, Sebastian

AU - Dixius, Andreas

PY - 2018/9/17

Y1 - 2018/9/17

N2 - Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more e^x components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

AB - Neuromorphic chips are used to model biologically inspired Spiking-Neural-Networks(SNNs) where most models are based on differential equations. Equations for most SNN algorithms usually contain variables with one or more e^x components. SpiNNaker is a digital neuromorphic chip that has so far been using pre-calculated look-up tables for exponential function. However this approach is limited because the memory requirements grow as more complex neural models are developed. To save already limited memory resources in the next generation SpiNNaker chip, we are including a fast exponential function in the silicon. In this paper we analyse iterative algorithms for elementary functions and show how to build a single hardware accelerator for exp and natural log, for a neuromorphic chip prototype, to be manufactured in a 22 nm FDSOI process. We present the accelerator that has algorithmic level approximation control, allowing it to trade precision for latency and energy efficiency. As an addition to neuromorphic chip application, we provide analysis of a parameterized elementary function unit that can be tailored for other systems with different power, area, accuracy and latency constraints.

KW - exponential function

KW - logarithm function

KW - hardware accelerators

KW - approximate arithmetic

KW - fixed-point arithmetic

KW - SpiNNaker2

KW - neuromorphic computing

KW - MPSoC

U2 - 10.1109/ARITH.2018.8464785

DO - 10.1109/ARITH.2018.8464785

M3 - Paper

SP - 37

EP - 44

T2 - 25th IEEE Symposium on Computer Arithmetic

Y2 - 25 June 2018 through 27 June 2018

ER -