An event-driven massively parallel fine-grained processor array

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A multi-core event-driven parallel processor array design is presented. Using relatively simple 8-bit processing cores and a 2D mesh network topology, the architecture focuses on reducing the area occupation of a single processor core. A large number of these processor cores can be implemented on a single integrated chip to create a MIMD architecture capable of providing a powerful processing performance. Each processor core is an event-driven processor which can enter an idle mode when no data is changing locally. An 8x8 prototype processor array is implemented in a 65 nm CMOS process in 1,875um x 1,875um. This processor array is capable of performing 5.12 GOPS operating at 80 MHz with an average power consumption of 75.4 mW.

Bibliographical metadata

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2015
ISBN (Electronic)978-1-4799-8391-9
Publication statusPublished - Jun 2015